Ryerson University Department of Electrical and Computer Engineering ELE 538 Microprocessor Systems Final Examination December 8, 2003

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1 Ryerson University Department of Electrical and Computer Engineering ELE 538 Microprocessor Systems Final Examination December 8, 23 Name: Student Number: Time limit: 3 hours Section: Examiners: K Clowes, V Geurkov Notes: a) Closed book except for 68HC Technical Data and/or Reference book b) No questions during exam period State any assumptions c) Answer neatly all questions in the space provided Unclear answers will not be accepted d) Circle your professor s name and hand in these sheets e) Use standard symbolic names for any internal registers (3 marks) Disassemble the following memory dump into 68HC assembly instructions: 6 DC 8B FE CB FD DD ORG $6 6 DC LDD $ 62 8B FE ADDA #$FE 64 CB FD ADDB #$FD 66 DD STD $ 2 (2 marks) How many memory chips are required to build a MB, 32-bit wide memory system using the 28K x 6 SRAM chips? Prove your answer With x 6 organization memory chips, 2 chips will be required to build a 32-bit memory system Two chips have a capacity of 28K x 32 bit = 52K x 8 bit = 52KB) Four chips will have a capacity of MB 3 (5 marks) Given the following memory dump: FA 6 FF FF A FF A A F 5 F 53 4E 7 E fill in the blanks in the following table: (Solution in a bold case) Address Contents Assembly Code Acc A Acc B NZVC (CCR) X-register Y-register SP (Stack Pointer) PC (Progr counter) 62 CE 6 2 LDX #$62 F2-62 FFFF EC LDD,X 67 FA - 62 FFFF SUBD #$45 67 B5 62 FFFF DD 56 STD $56 67 B5 62 FFFF 4 62A 62A A6 7 LDAA 7,X 66 B5 62 FFFF 4 62C 62C F3 6 3E ADDD $63E D FFFF 4 62F 62F 5F CLRB D7 62 FFFF 4 62

2 - 2-4 (4 marks) You have been assigned to design an 8-bit 68HC-based system with 64KB memory space The system will have one external 2KB x 8 EPROM chip, two external KB x 4 RAM chips, 256B of internal RAM, and one 8-bit I/O device Make the memory space assignment and design the address decoder The address must reside in the internal RAM A5 A4 A A 2-to-4 Decoder Y Y Y2 A3 A2 EPROM 6K x 8 D7 Y3 A D A2 A A RAM 8K x 4 A2 A A RAM 8K x 4 I/O device I/O register Internal RAM: $ ~ $3FFF (INIT register must contain eg $2) External EEPROM: $4 ~ $7FFF External RAM: $8 ~ $B5FF Internal EEPROM: $B6 ~ $B7FF External RAM: $B8 ~ $BFFF I/O device: $C ~ $DFFF Internal ROM: $E ~ $FFFF

3 - 3-5 (5 marks) A 68HC computer input-output system must be designed (see Figure below) The system represents a modulo-4 up-counter, which counts the number of pulses on the port A ($) pin PA2 The circuit must be able to react to all changes in the input signal; thus it must take specific action at both the positive and negative edges of each pulse A 7-segment display indicates the number of pulses that have been received modulo-4 (a) Draw a state diagram for this sequence of events (b) Write the 68HC code to accomplish this Buffer Chip a b g $4 V CC PB6 PB5 PA7 68HC PB common cathode PA2 PA Figure (a): A/ B/ C/ D/2 H/ G/3 F/3 E/2

4 (b): STATE RMB State assignment: REGBAS EQU $ PORTA EQU $ A - $ PORTB EQU $4 B - $ C - $2 LDX #REGBAS D - $3 SA LDAA #$ E - $4 F - $5 G - $6 BRCLR PORTA, X $4 SB H - $7 BRA SA SB LDAA #$ BRSET PORTA, X $4 SC BRA SB SC LDAA #$2 BRCLR PORTA, X $4 SD BRA SC SD LDAA #$3 BRSET PORTA, X $4 SE BRA SD SE LDAA #$4 BRCLR PORTA, X $4 SF BRA SE SF LDAA #$5 BRSET PORTA, X $4 SG BRA SF SG LDAA #$6 DISPLASTATE LDAB STATE LDY #DIS ABY BRCLR PORTA, X $4 SH LDAB,Y BRA SG STAB PORTB, X RTS SH LDAA #$7 DIS FCB $7E, $3, $3, $6D FCB $6D, $79, $79, $7E BRSET PORTA, X $4 SA BRA SH

5 - 5-6 ( marks) The circuit in Figure 2 is designed to measure the room temperature The temperature is to be displayed in two integer digits on the CRT-display, which supports RS-232 interface standard and accepts ASCII symbols The readings on the display are to be updated once per second The room temperature never goes below O C and never goes above 42 O C so that the A/D converter of the 68HC can be used to perform the conversion as well as to transmit the result through the serial communication interface Write the assembly code to accomplish this task Notes: (a) the output compare 2 (OC2) function must be used to create a delay of second; (b) the display is able to receive 8 bits per frame at a rate of 48 bps (E-clock is MHz); (c) assume that the display is smart enough to position the 2-digit group of the ASCII-symbols received to the same place of the screen 68HC ASCII symbols to the CRT-display TxD V RH V RL AN Figure 2 5 V V Analog signal from the conditioning circuit ( 5 v) REGBAS EQU $ BAUD EQU $2B SCCR EQU $2C SCCR2 EQU $2D SCDR EQU $2F SR EQU $2E TOC2 EQU $8 TFLG EQU $23 OPTION EQU $39 ADCTL EQU $3 OC2M EQU $BF TCNT EQU $E BYTE RMB BYTE2 RMB OC2CNT RMB LDX #REGBAS LDAA #$3 STAA BAUD, X LDAA # STAA SCCR, X (8 bits) LDAA #$2C STAA SCCR2, X (receivintenab,te,re) BSET OPTION, X $8 (enab A/D) BCLR OPTION, X $4 (sele-clk) LDY #3 (delay 5 μs) DEL DEY BNE DEL FOREV LDAA # STAA ADCTL, X (nonscan, single chan, AN) HERE LDAA ADCTL, X BPL HERE LDAB ADR, X (B = A/D result)

6 - 6 - CLRA LDX #6 IDIV XGDX LDX # IDIV (lower digit in B, upper in X) ADDB #$3 (ASCII conversion) STAB SCDR, X BRCLR SR, X $8 * XGDX ADDB #$3 (ASCII conversion) STAB SCDR BRCLR SR, X $8 * LDAB # STAB OC2CNT LDX #REGBAS BCLR TFLG, X OC2M LDD TCNT, X REP ADDD $2 STD TOC2, X WAIT BRCLR TFLG, X $4 * BCLR TFLG, X OC2M LDD TOC2, X DEC OC2CNT BNE REP JMO FOREV END 7 (6 marks) Write a program to measure the pulse width of the unknown signal that is connected to the IC2 pin Return the pulse width in D Assume the main timer prescale factor is and the pulse width is shorter than 2 ms The E-clock frequency is 2 MHz REGBAS EQU $ TFLG EQU $23 TIC2 EQU $2 TCLT2 EQU $2 TMSK EQU $22 EDG-CNT MB EDGE RMB PUL-WID RMB 2 WAIT TST EDGE-CNT BNE WAIT ORG $FFE8 LDD TIC2, X JMP ISR SUBD EDGE STD PUL-WID ORG $6 SWI LDX #REGBAS LDAA #$2 ISR LDX #REGBAS STAA TFLG, X BCLR TFLG, X $FD LDAA #$C DEC EDGE-CNT STAA TCTL2, X BEQ SKIP LDAA #2 LDD TIC2, X STAA EDG-CNT STD EDGE BSET TMSK, X $2 SKIP RTI CLI END

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