COTS Multicore Processors in Avionics Systems: Challenges and Solutions

Transcription

1 COTS Multicore Processors in Avionics Systems: Challenges and Solutions Dionisio de Niz Bjorn Andersson and Lutz Wrage

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4 Why Multi-Core Processors? Processor development trend Increasing overall performance by integrating multiple cores Embedded systems: Actively adopting multi-core CPUs Automotive: Freescale i.mx6 4-core CPU NVIDIA Tegra K1 platform Avionics and defense: Rugged Intel i7 single board computers Freescale P core CPU 3

5 Shared Hardware: Multicore Memory System Core 1 L1/L2 Core 2 L1/L2 Core 3 L1/L2 Core N L1/L2 Last-Level Cache (L3) Memory Bus (and Mem Controller) DRAM Bank 0 DRAM Bank 1 DRAM Bank 2 DRAM Bank 2 DRAM Bank B 4

6 Cache Interference Across Cores X Core 1 XY Y Core 2 Cache 5

7 Bank Interference Across Cores BANK columns Core 1 X Y Z A B C rows Core 2 AX BY CZ 6

8 Impact of Memory Interference 1 attacker Max 5.5x increase 2 attackers Max 8.4x increase 3 attackers Max 12x increase We should predict, bound and reduce the memory interference delay! Norm. execution time (%) blackscholes bodytrack 12x increase observed canneal ferret fluidanimate freqmine raytrace streamcluster swaptions vips x264 7

9 Cache / Bank Partitioning (Coloring) Main Mem Virtual Pages Cache Set 8

10 Cache / Bank Partitioning (Coloring) Main Mem Banks Virtual Pages 9

11 Cache / Bank Partitioning (Coloring) Main Mem Set associativity Virtual Pages Cache Address bits Cache sets One page 6 Cache Index 10

12 Cache and Bank Address Bits Cache Index Address bits XOR XOR XOR Bank Index E.g. 2 bank bits 2 cache bits 1 shared bit 11

13 Coordinated Cache and Bank Partitioning (Private Partitions) Avoid conflicting color assignments Take advantage of different conflict behaviors Banks can be shared within same core but not across cores Cache cannot be shared within or across cores Take advantage of sensitivity of execution time to cache Task with highest sensitivity to cache is assigned more cache Diminishing returns taken into account Two algorithms explored Mixed-Integer Linear Programming Knapsack 12

14 Experimental Results 180% 170% 160% Cache coloring only Our coordinated approach 150% 140% 130% 120% 110% 100% 90% 80% PS.canneal PS.ferret PS.streamcluster PS.fluidanimate PS.facesim PS.freqmine PS.x264 SPEC.leslie3d SPEC.mcf SPEC.milc SPEC.sphinx3 13

15 Shared Bank Partitioning Explicitly considers the timing characteristics of major DRAM resources Rank/bank/bus timing constraints (JEDEC standard) Request re-ordering effect Bounding memory interference delay for a task Combines request-driven and job-driven approaches Task s own memory requests Interfering memory requests during the job execution Software DRAM bank partitioning awareness Analyzes the effect of dedicated and shared DRAM banks 14

16 DRAM Organization DRAM Rank Command bus Address bus Data bus 64-bit CHIP 1 8-bit CHIP 2 CHIP 3 CHIP 4 CHIP 5 CHIP 6 CHIP 7 CHIP 8 DRAM Chip Bank 8 Bank... Bank 1 Columns Command bus Address bus Data bus Command decoder 8-bit Row address Row decoder Column address Row buffer Column decoder Rows Row hit Row conflict DRAM access latency varies depending on which row is stored in the row buffer 15

17 Memory Controller Memory requests from CPU cores Processor data bus Request buffer Bank 1 Priority Queue Bank 2 Priority Queue... Bank n Priority Queue Memory scheduler Bank 1 Scheduler Bank 2 Scheduler... Bank n Scheduler Read/ Write Buffers Two-level hierarchical scheduling structure Channel Scheduler DRAM address/command buses DRAM data bus 16

18 Memory Scheduling Policy FR-FCFS: First-Ready, First-Come First-Serve Goal: maximize DRAM throughput Maximize row buffer hit rate Bank 1 Scheduler Bank 2 Scheduler... Bank n Scheduler 1. Bank scheduler Considers bank timing constraints Prioritizes row-hit requests In case of tie, prioritizes older requests Channel Scheduler 2. Channel scheduler Considers channel timing constraints Prioritizes older requests Memory access interference occurs at both bank and channel schedulers Intra-bank interference at bank scheduler Inter-bank interference at channel scheduler 17

19 DRAM Bank Partitioning Prevents intra-bank interference by dedicating different DRAM banks to each core Can be supported in the OS kernel (1) w/o bank partitioning Core 1 Core 2 (2) w/ bank partitioning Core 1 Core 2 Bank 1 Scheduler Bank 2 Scheduler Bank 1 Scheduler Bank 2 Scheduler Channel Scheduler Channel Scheduler Intra-bank and inter-bank interference Only inter-bank interference 18

20 Bounding Memory Interference Delay 1. Request-Driven Bounding 2. Job-Driven Bounding Response-Time Based Schedulability Analysis 19

21 Response-Time Test Memory interference delay cannot exceed any results from the RD and JD approaches We take the smaller result from the two approaches Extended response-time test Classical iterative response-time test Request-Driven (RD) Approach Job-Driven (JD) Approach 20

22 Experiment Severe Memory Interference Private DRAM Bank Norm. Response Time (%) Observed Predicted 4.1x increase DRAM bank partitioning helps reducing the memory interference 0 blackscholes bodytrack canneal ferret fluidanimate freqmine raytrace streamcluster swaptions vips x264 Our analysis enables the quantification of the benefit of DRAM bank partitioning 21

23 Non-Severe Memory Interference Private DRAM Bank Norm. Response Time (%) Observed Predicted blackscholes bodytrack Average over-estimates are 8% (13% for a shared bank) canneal ferret fluidanimate freqmine raytrace streamcluster swaptions vips x264 Our analysis bounds memory interference delay with low pessimism under both high and low memory contentions 22

24 Implementation Cache and Bank Partitioning implemented in Linux/RK Associates Resource Reservations to Linux Threads Memory reservation Cache reservation CPU reservation Portable Kernel Module Hooks into on-demand page allocation At boot time create large memory reserve Pages are classified in cache and bank colors 23

25 Model Problem Ball-following Controller on Odroid+Linux/RK Memory interference Fixed distance Ball-Following: Keep fixed distance as ball moves around 24

26 Experimental Results (1) ~ Frame Processing (no protection, no attackers)...,. J : - -<'--~.:~-~~ ' \.:.- c._..-:&.: :r. I I I I Time [s] Frame inter- arrival time Frame processing time Software Engineering Institute I Ca.rnegieMellon 25

27 Experimental Results (2) 0.4- Frame Processing (no protection, 3 attackers) l- n en an ann s nn a en w s a t111eo sa a 6 U 7 T&LlP 7 7 A S,..., (J)... E o I 0 I I I Time [s] Frame inter- arrival time Frame processing time Deadlines misses at 0.2. only 195 out of 279 frames processed (30% loss) Software Engineering Institute I CarnegieMellon 26

28 Experimental Results (3) l- Frame Processing (with protection, 3 attackers) " IS - tf - e ~t'.t r nlv -:,. t:+:ja 4ki'Dztcl OtPCUsloutJ'tlt& Jtl,.-...,..., (J)... E o I I I I Time [s] Frame inter- arrival time Frame processing time No deadline misses. Processing below 0.2 s interarrival (period) Software Engineering Institute I CamegieMellon 27

29 Concluding Remarks Multicore processor challenges previous results in real-time systems Interference from shared hardware Cache, Memory banks, Memory bus Leads to less usable processing capacity 1200% increase in a four core machine (92% reduction from single core) Our approach Coordinated private partitions for cache and memory Shared bank partitions Implemented in Linux/RK Experimental results for model avionics application Protects control algorithm from interference 28