easic Technology & Nextreme Architecture

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Trevor Matthews
6 years ago
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1 easic Technology & Nextreme Architecture Tomer Kabakov Director of Sales Tel:

2 easic at a Glance Fabless Semiconductor Company Provider of Structured ASIC Products Founded in 1999 Headquarters in Santa Clara, California R&D facilities in Romania and Malaysia Worldwide sales and design support teams Shipping chips to customers and generating revenues Private company, funded by venture capital firms and private investors (including: Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners)

3 The easic Advantage Affordable Customization ~40 unique layers Large upfront cost ($25M) 18 month design cycle 48% probability of respin 12 week turn-around Expensive design tools No unique layers High power High unit cost The Advantage One unique layer Small upfront costs ($K) 2 month design cycle Low respin probability 4 week turn-around Low tools cost Ability to differentiate Create multiple derivatives Up to 20% of the power Up to 40% of the cost

4 Nextreme Structured ASIC Introduction Up to 358K Logic ecells Up to 790 User I/Os Up to 5.6Mbits of bram Configurable I/Os Up to 5.6Mbits of eram 1.2V, 1.3V Core Options Up to 8 PLLs No Minimum Quantity 4-weeks from Tapeout to Silicon No Mask Charges

5 Nextreme Design Win Sample Cell phone Projector Security Video Surveillance Broadcast Camera NVR/DVR Military Communications Multi-computing Image Processing Wireless Basestations Instrumentation Gateways

At Last an ASIC Alternative to FPGA Can you give up multiple times electrically reprogrammable for: A chip that is 10% to 60% the unit price of an FPGA 10% the power of an FPGA Up to 4x

6 At Last an ASIC Alternative to FPGA Can you give up multiple times electrically reprogrammable for: A chip that is 10% to 60% the unit price of an FPGA 10% the power of an FPGA Up to 4x performance improvement over an FPGA How? - Late stage via and bit stream structured ASIC NX750 (90nm) 55K ecells ~800K Gates Drawn to Scale Virtex-4 (90nm) XCVLX60 53K Logic Cells ~800K Gates

7 Nextreme: Disruptive Technology easic s Divide and Conquer customization method: Logic is customized with Bit-stream or with single Via-mask Routing is customized with single Via-mask or - maskless (ebeam) 7

8 Time to Production Breakthrough SL Reprogrammable LUT Maximum flexibility Shortest turnaround time Ideal for prototypes OR VL Fixed LUT No external bitstream Instant On No inrush current Ideal for production Identical Devices Two Tape-out Options

9 Low Manufacturing Cost and Risk No Minimum Order Quantity Wafer Sharing Prototypes for Design A Low Volume Production for Design B Low Volume Production for Design C 4-week Turnaround Higher Volume Production for Design D

10 Nextreme Family Details Gates* ecells Distributed RAM (Max.) eram eram Block RAM bram bram PLLs Max. User I/O Blocks Bits Blocks Bits NX750LP 350,000 26, K K NX ,000 55, K K NX1500 1,500, , K K NX2500 2,500, , K K NX4000 4,000, , K K NX5000 5,000, , K K * Combination of Logic and Memory

11 Static Power Comparison Standby Power S180 LX220 LX330 SL340 Altera Stratix II Altera Stratix III 0.9V Xilinx Virtex 5 LX Xilinx Virtex 4 LX easic Nextreme NX Hardcopy 1 Hardcopy 2 Power (W) S60 S90 S130 LX110 SL110 SL200 LX200 SL150 LX160 HC240 Sources: easic: Nextreme Power Estimator easic: NX1500 NX5000 Measured Altera: PowerPlay Early Power Estimator Xilinx: XPower Early Power Estimator Notes: a. 1 Altera Logic Element = 1 Xilinx Logic Cell = 1 easic ecell b. Typical Conditions LX100 S30 LX30 HC1S25 LX60 HC210 NX750 LX80 HC220 HC1S80 NX1500 HC230 NX2500 NX4000 NX5000 Logic Elements

12 Dynamic Power Comparison 80K LC/LE/eCells 12.5% Activity Typical Conditions Virtex 4 Stratix-II Hardcopy Virtex 5 Stratix-III Hardcopy 2 Nextreme

13 Video Processing Power Consumption Bake-off easic Power Supply Video Camera Virtex Power Supply Fan Nextreme NX4000 VL Xilinx Virtex-4 LX200 easic Board FPGA Board 13

14 Nextreme 13X to 15X Lower Power Than FPGAs Virtex-4 LX200 FPGA Nextreme NX4000 VL Structured ASIC Power Consumption Improvement Using Nextreme Static Power: No Clocks 768 mw 120 mw 6X Total Power: RGB Filter (Algorithm 1) RGB Filter (Algorithm 2) RGB Filter (Algorithm 3) RGB Filter (Algorithm 4) 4.8 W 360 mw 13X 5.83 W 420 mw 14X 5.66 W 370 mw 15X 5.72 W 380 mw 15X 14

15 Nextreme Architecture 15

16 Nextreme Technology; ecell ecell Components 2x 3-input LUT 2x 2-input NAND MUX DFF Output drivers Configuration jumpers 16

17 Nextreme Hierarchy - ecore and bram ecell eunit (256 ecells) U3 U1 X Decoder U4 U2 ecore (8 eunits) Y Decoder Y Decoder + U5 U6 U7 X Decoder U8 bram 32Kbits of bram Configurable as 1K x 32 2K x 16 4K x 8 8K x 4 16K x 2 32K x 1 can be configured as logic or 16-bits eram 256 ecells or 4Kb eram 2048 ecells or 32Kb eram

18 Nextreme Technology; Device Layout ecore Global Clocks bram ecorerow eiobank emµ 18

19 Nextreme Summary Low Development Cost No Mask Charges No MOQ Free Diamond Processors FPGA like Tool Cost Structured ASIC Custom Logic Performance HD Encoding in Hardware capabilities ARM926 at 175MHz Low Power In battery applications today 10-20X lower power than FPGAs IDE IDE X8 PCI Express X8 PCI Express JPEG2000 HD H.264 Enc. Dec Image Enhancement USB2.0 OTG PCI DDR2 Rapid Changes/Derivatives 2-6 week design turn 4 weeks manufacturing Rapid software changes using Diamond Processors Cost Competitive ARM926EJ AHB Arbiter/Timer/GPIO DCT idct SATA 10/100/1G Time to Market Cell-based ASIC like unit cost Simple FPGA like design flow IP library: Diamond Processors, peripherals, interfaces etc. Industry standard µp tools/kits

20 Thank You 20

Field Programmable Gate Array (FPGA) Devices

Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs