82439TX System Controller (MTXC) SmartDie Product Specification

Transcription

1 Preliminary 82439TX System Controller (MTXC) SmartDie Product Specification Supports the Pentium Processor Family Host Bus at 66 MHz and 60 MHz at 3.3 V and 2.5 V PCI 2.1 Compliant Integrated Data Path Integrated DRAM Controller 4 Mbytes to 256 Mbytes Main Memory 64-Mbit DRAM/SRAM Technology Support FPM (Fast Page Mode), EDO, and SDRAM DRAM support 6 RAS Lines Available Integrated Programmable Strength for DRAM Interface CAS-Before-RAS Refresh, Extended Refresh and Self Refresh for EDO CAS-Before-RAS and Self Refresh for SDRAM Integrated L2 Cache Controller 64 Mbyte DRAM Cacheability Direct Mapped Organization Write Back Only Supports 256 Kbyte and 512 Kbyte Pipelined Burst SRAM and DRAM Cache Cache Hit Read/Write Cycle Timings at Back-to-Back Read/Write Cycles at K x 32 SRAM Also Supported Fully Synchronous, Minimum Latency 30/33 MHz PCI Bus Interface Five PCI Bus Masters (Including PIIX4) 10 DWord PCI-to-DRAM Read Prefetch Buffer 18 Dword PCI-DRAM Post Buffer Multi-Transaction Timer to Support Multiple Short PCI Transactions Power Management PCI CLKRUN# Support Dynamic Stop Clock Support Suspend to RAM (STR) Suspend to Disk (STD) Power On Suspend (POS) Internal Clock Control SDRAM and EDO Self Refresh During Suspend ACPI Support Compatible SMRAM (C-SMRAM) and Extended SMRAM (E-SMRAM) SMM Write-Back Cacheable in E_SMRAM Mode up to 1 Mbyte 3.3/5 V DRAM, 3.3/5 V PCI, 3.3/5 V Tag, and 3.3/2.5 V SRAM Support Test Features NAND Tree Support for All Pins Supports the Universal Serial Bus (USB) Intel SmartDie Product Full AC/DC Testing at Die Level 0 C to 105 C (Junction) Temperature Range NOTICE: This document contains preliminary information on new products in production. It is valid for the devices indicated in "DEVICE NOMENCLATURE" on page 16. This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest product specification before finalizing a design. REFERENCE INFORMATION: The information in this document is provided as a supplement to the standard package datasheet on a specific product. Please refer to the standard package datasheet (order number ) for product information and specifications not found in this document. INTEL CORPORATION, 1997 August 1997 Order Number:

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL or call INTEL CORPORATION, 1997

3 Contents 82439TX System Controller (MTXC) SmartDie Product Specification 1.0 DIE SPECIFICATIONS INTEL DIE PRODUCTS PROCESSING Test Procedure Wafer Probe Wafer Saw Die Inspection Packing Procedure Inspection Steps Storage Requirements Electro-Static Discharge (ESD) SPECIFICATIONS Physical Specifications DC Specifications DEVICE NOMENCLATURE REFERENCE INFORMATION REVISION HISTORY FIGURES Figure TX System Controller Die Photo... 1 Figure TX System Controller Die/Bond Pad Layout... 2 TABLES Table TX System Controller Bond Pad Center Data... 3 Table TX System Controller Physical Specifications Preliminary iii

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5 1.0 DIE SPECIFICATIONS The die photo in Figure 1 and the plot in Figure 2 indicate the orientation of the die in the GEL-PAK* (shipping container). Die are aligned as shown relative to a 45 notch which is in one corner of the GEL-PAK. An Intel internal manufacturing name 88TX1A appears on the die. Table 1 describes the bond pad number and pad center data for each signal. Figure TX System Controller Die Photo Preliminary 1

6 Gel-Pak Notch NC LOCK# AD28 FRAME# AD25 IRDY# AD22 AD24 V CC REQ0# AD20 TRDY# GNT0# DEVSEL# REQ1# C/BE2# V CC AD13 AD11 GNT1# AD8 C/BE0# AD7 AD3 AD4 STOP# AD0 V CC PAR REQ3# MD13 GNT3# MD45 MD15 MD12 V REF MD30 V CC V CC HD61 HD62 HD60 HD57 HD59 HD50 HD58 HD53 HD43 HD54 HD49 HD47 HD52 HD46 HD48 HD38 HD45 HD39 BE1# BE0# HD34 BE5# BE3# AHOLD HD32 HD30 HD29 HD23 HD26 HD25 HD7 HD28 HD19 HD24 HD17 HD18 HD20 HD6 HD4 HD16 HD5 V CC CPU V CC CPU V CC CPU V CC CPU V CC 4 HD53 HLOCK# HD63 M/IO# HD56 HD58 HD51 HD55 V CC CPU HD44 CACHE# HD41 KEN# HD40 HD42 HD36 HD37 BE2# BE6# BE4# 46 V CC CPU HD33 BE7# HD27 HD35 BRDY# HD31 NA# HD21 HD12 HD8 HD22 BOFF# HD14 EADS# HD15 ADS# NC 85 AD30 PHLD# AD31 AD28 PHLDA# AD26 AD23 HD10 HD0 HD2 HD13 A20 D/C# HD9 AD27 AD19 C/BE3# 88TX1A M C 1996 AD21 AD16 AD17 AD18 AD15 C/BE1# AD14 AD12 PCLKIN AD10 AD9 REQ2# AD6 AD5 X82439Tx AD1 GNT2# AD2 CLKRUN# MD31 MD14 MD47 MD29 M C 88TX1A 1996 MD63 MD61 MD46 MD60 MD28 MD27 MD43 MD62 MD59 MD44 MD58 MD42 MD25 MD57 MD24 MD9 MD56 MD32 MD19 MD18 MD36 MD50 MD4 MD5 MD23 MD55 MD54 MD39 MD6 MD38 MD22 MD20 MD51 SCASB# MD53 MD11 SCASA# SUSCLK RAS3# CAS4# CAS6# CAS5# RAS2# CAS2# CAS0# CAS3# RAS0# MWEB3 HITM# HD1 A19 A16 A14 HD11 HD3 A12 V CC CPU A18 A5 A9 A17 A15 W/R# A11 A13 A8 SMIACT# A31 A21 A23 A10 A25 A7 A27 A26 A22 A24 A29 A28 A30 A3 CC V CPU A4 A6 CADV# COE# BWE# TWE# CCS# CADS# GWE# TIO3 TIO1 TIO6 TIO7 TIO2 CC TIO4 V TIO5 MA5 TIO0 MA2 MA0 MA4 SS MA1 V CKEB MA3 TEST MA10 KRQ4K RST# MA7 MA6 NC MA11 MA9 V SS MA8 255 NC MD49 MD10 MD48 MD26 MD35 MD41 MD33 MD8 V CC MD40 MD16 MD0 MD1 MD2 MD17 MD52 HCLKIN MD7 MD34 MD3 V CC MD37 SRASB# V CC MD21 SRASA# RAS5# SUS_STAT# RAS1 CKE MWE# CAS2# V CC (SUS) RAS4# V CC SUS CAS1 V CC (SUS) V CC V CC A Figure TX System Controller Die/Bond Pad Layout 2 Preliminary

7 Table TX System Controller Bond Pad Center Data (Sheet 1 of 11) 1 V CC CPU V CC CPU V CC HD HD HD HD HLOCK# HD HD HD M/IO# HD HD HD HD HD HD HD V CC CPU HD HD HD CACHE# HD HD HD KEN# HD HD HD Preliminary 3

8 Table TX System Controller Bond Pad Center Data (Sheet 2 of 11) 32 HD HD HD HD BE1# HD BE0# BE2# HD BE6# BE5# BE4# BE3# V CC CPU AHOLD HD HD BE7# HD HD HD HD HD BRDY# HD HD HD NA# HD HD HD Preliminary

9 Table TX System Controller Bond Pad Center Data (Sheet 3 of 11) 64 HD HD HD HD HD HD HD BOFF# HD HD HD EADS# HD HD HD ADS# HD NC V CC CPU V CC CPU HD HD A HD D/C# HD HD Preliminary 5

10 Table TX System Controller Bond Pad Center Data (Sheet 4 of 11) 96 HD HITM# A A HD A A HD A V CC CPU A A A A A W/R# A A A SMIACT# A A A A A A A A A A A Preliminary

11 Table TX System Controller Bond Pad Center Data (Sheet 5 of 11) 128 A A A V CC CPU A CADV# COE# BWE# CCS# TWE# GWE# CADS# TIO TIO TIO TIO TIO V CC TIO TIO TIO MA MA MA MA CKEB MA TEST MA MA KRQAK Preliminary 7

12 Table TX System Controller Bond Pad Center Data (Sheet 6 of 11) 160 MA RST# MA MA MA NC MA V CC V CC V CC (SUS) MWEB# RAS0# CAS1# CAS3# V CC (SUS) CAS0# RAS4# CAS2# V CC (SUS) RAS2# CAS7# CAS5# MWE# CAS6# CKE CAS4# RAS1# RAS3# Preliminary

13 Table TX System Controller Bond Pad Center Data (Sheet 7 of 11) 192 SUS_STAT1# SUSCLK RAS5# SCASA# SRASA# MD MD MD V CC SCASB# SRASB# MD MD MD MD V CC MD MD MD MD MD MD MD HCLKIN MD MD MD MD MD MD Preliminary 9

14 Table TX System Controller Bond Pad Center Data (Sheet 8 of 11) 224 MD MD MD MD MD MD MD MD MD MD V CC MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD MD NC Preliminary

15 Table TX System Controller Bond Pad Center Data (Sheet 9 of 11) 256 V CC V CC MD MD MD MD V REF MD MD MD MD MD MD MD MD GNT3# MD MD MD REQ3# MD PAR MD V CC CLKRUN# AD AD STOP# GNT2# AD Preliminary 11

16 Table TX System Controller Bond Pad Center Data (Sheet 10 of 11) 288 AD AD AD AD AD C/BE0# REQ2# AD AD GNT1# AD AD PCLKIN AD AD V CC AD C/BE1# C/BE2# AD REQ1# AD DEVSEL# AD GNT0# AD TRDY# AD AD C/BE3# REQ0# Preliminary

17 Table TX System Controller Bond Pad Center Data (Sheet 11 of 11) 320 AD V CC AD AD AD AD AD IRDY# PHLDA# AD AD FRAME# AD AD PHLD# LOCK# AD NC Preliminary 13

18 2.0 INTEL DIE PRODUCTS PROCESSING 2.1 Test Procedure Intel has instituted full-speed functional testing at the die level for all SmartDie products. This level of testing is ordinarily performed only after assembly into a package. Each die is tested to the same electrical limits as the equivalent package unit. 2.2 Wafer Probe Wafer probing is performed on every wafer produced in Intel Fabs. The process consists of specific electrical tests and device-specific functionality tests. At the wafer level, built-in test structures are probed to verify that device electrical characteristics are in control and meet specifications. Measurements are made of transistor threshold voltages and current characteristics; poly and contact resistance; gate oxide and junction integrity; and specific parameters critical to the particular technology and device type. Wafer-to-wafer, across-the-wafer run-to-run variation and conformance to spec limits are checked. The actual devices on each wafer are then probed for both functionality and performance to specifications. Additional reliability tests are also included in the probe steps. 2.3 Wafer Saw Probed wafers are transferred to Intel s assembly sites to be sawed. The saw cuts totally through the wafer. 2.4 Die Inspection Upon completion of the wafer saw, the die are moved to pick and place equipment that removes reject die. The remaining die are submitted to the same visual inspection as standard packaged product. The compliant die are then transferred to GEL-PAKs for shipment. 2.5 Packing Procedure Intel will ship all Intel die products in GEL-PAKs. GEL PAKs eliminate the die edge damage usually associated with die cavity plates or chip trays. The backside of each die adheres to the gel membrane in the GEL-PAK, eliminating the risk of damage to the active die surface. A simple vacuum release mechanism allows for pick and place removal at the customer s site. Only die from the same wafer lot are packaged together in a GEL-PAK, and all die are placed in the GEL-PAK with a consistent orientation. The GEL- PAKs are then sealed and labeled with the following information: Intel Smart Die Intel Part Number Assembly Process Order/Spec ROM Code (if applicable) Customer Part Number (if applicable) Assembly Lot Traveler Number Finished Product Order Number Quantity Seal Date Country of Origin NOTE: GEL-PAKs require a Vacuum Release Station. Contact Vichem* Corporation for more information. 2.6 Inspection Steps Multiple inspection steps are performed during the die fabrication and packing flow. These steps are performed according to the same specifications and criteria established for Intel s standard packaged product. Specific inspection steps include a wafer saw visual as well as a final die visual just before die are sealed in moisture barrier bags. 2.7 Storage Requirements Intel die products will be shipped in GEL-PAKs and sealed in a moisture-barrier anti-static bag with a desiccant. No special storage procedures are required while the bag is still unopened. Once opened, the GEL-PAK should be stored in a dry, inert atmosphere to prevent corrosion of the bond pads. 2.8 Electro-Static Discharge (ESD) Components are ESD sensitive. 14 Preliminary

19 3.0 SPECIFICATIONS Specifications within this document are specific to a particular die revision and are subject to change without notice. Verify with your local Intel Sales Office that you have the latest data before finalizing a design. 3.1 Physical Specifications Table 2 defines the 82439TX System Controller physical specifications. Table TX System Controller Physical Specifications Die Revision: A-2 Step Post-Saw Die Dimensions: Mils: X = ± 0.5, Y= ± 0.5 See associated Die/Bond Pad Layout for X, Y orientation. Die Thickness: 17 ± 1 mils Minimum Pad Pitch: 60/120 microns (see die plot for more detail) Pad Passivation Opening Size: : 95 x 95 (Note: pad size is not perfect square) Bond Pad Metallization: (outermost layer first) 14,000 Angstroms Aluminum (0.5% Copper), 1000 Angstroms Titanium Pads per Die: 340 Die Backside Material: 1600 Angstroms Gold, 150 Angstroms Chrome (outermost layer first) Passivation: 3.3 microns polyimide, 4500 Angstroms nitride (outermost layer first) Intel Fabrication Process: CMOS 3.2 DC Specifications ABSOLUTE MAXIMUM RATINGS GEL-PAK Storage Temperature...0 C to +70 C Junction Temperature Under Bias C to +110 C OPERATING CONDITIONS T J (Junction Temperature Under Bias)... 0 C to 105 C (1) Substrate Bias... Float (Self Biasing to ), Alternative is to Drive Core Operating Frequency...60, 66 MHz 1. Average die surface temperature NOTICE: This datasheet contains preliminary information on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. Verify with your local Intel Sales Office that you have the latest data before finalizing a design. WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and extended exposure beyond the Operating Conditions may affect device reliability. Preliminary 15

20 4.0 DEVICE NOMENCLATURE X T X Package Type X = Die Base Product Number VALID COMBINATIONS: X82439TX 5.0 REFERENCE INFORMATION Document Title Order # 82439TX System Controller (MTXC) datasheet REVISION HISTORY Revision Date Description 002 8/97 In Table 1, the labels for Mils and were reversed and are correct in this revision. (Revision 001 showed the Mils data with the label and vice versa.) 001 2/97 Initial Release 16 Preliminary