UNIT 2 PROCESSORS ORGANIZATION CONT.

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1 UNIT 2 PROCESSORS ORGANIZATION CONT.

2 Types of Operand Addresses Numbers Integer/floating point Characters ASCII etc. Logical Data Bits or flags

3 x86 Data Types Operands in 8 bit -Byte 16 bit- word 32 bit- double word 64 bit- quad word 128 bit -double quadword

4 Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control

5 Data Transfer Specify Source Destination Amount of data Use for copy the contents from one register to another register.

6 Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point? May include Increment (a++) Decrement (a--) Negate (-a)

7 Shift and Rotate Operations

8 Logical Bitwise operations AND, OR, NOT

9 E.g. Binary to Decimal Conversion

10 RISC and CISC Microprocessor RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

11 Features of RISC m/c Limited and simple instruction set. Large no. of general purpose registers & use of compiler technology to optimize register usage. Simple instruction pipelining is used. A Single chip processor On chip cache and floating point processor.

12 Features of CISC m/c Instruction set with 120 to 350 instructions. Variable instructions and data formats. Small set of (8to24) general purpose registers. A large no of addressing modes

14 Architecture of typical RICS µp There are 9 functional units are interconnected by multiple data paths. Data paths are ranging from bit wide. Separate data and instruction caches are with separate data paths. BUS control unit controls and coordinates data transfer between chip and outside the architecture.

15 MMU(MEMORY MANAGEMENT UNIT) Perform all OPERATION RELATED TO MEMORY. There are two floating point units namely, multiplier unit and adder unit they can be use parallel. Graphical unit responsible for bit pixel data type. This unit supports 3D drawing in graphics frame buffer with colors and shade operations

16 Distinguish between RISC & CISC RISC Si ple, less u er of instructions are use Fi ed le gth instructions Co ple it i o piler O l LOAD/STORE instructions access memory. Few addressi g odes. CISC Ma o ple instructions Varia le le gth instructions Co ple it i microcode Ma i stru tio s a access memory Ma addressi g modes

17 REGISTER ORGANIZATION OF 8086 It is a 16-bit μp has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It requires +5V power supply is designed to operate in two modes, Minimum and Maximum. Memory Address ranges from 00000H to FFFFFH. 17

18 Intel 8086 Internal Architecture 18

19 Internal architecture of has two blocks BIU and EU. The BIU handles all transactions of data and addresses on the buses for EU. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. 19

20 BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. 20

21 EXECUTION UNIT Decodes instructions fetched by the BIU Generate control signals, Executes instructions. The main parts are: Control Circuitry Instruction decoder ALU 21

22 Register organization in 8086 µp 15 0

23 8086 Microprocessor Bus Interface Unit (BIU) Architecture Segment Registers Code Segment Register 16-bit CS contains the base or start of the current code segment. 23

24 8086 Microprocessor Bus Interface Unit (BIU) Architecture Segment Registers Data Segment Register 16-bit Points to the current data segment; operands for most instructions are fetched from this segment. The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit displacement are used as offset for computing the 20-bit physical address. 24

25 8086 Microprocessor Bus Interface Unit (BIU) Architecture Segment Registers Stack Segment Register 16-bit Points to the current stack. The 20-bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer (SP) for stack instructions such as PUSH and POP. 25

26 8086 Microprocessor Bus Interface Unit (BIU) Architecture Segment Registers Extra Segment Register 16-bit Points to the extra segment in which data (in excess of 64K pointed to by the DS) is stored. String instructions use the ES and DI to determine the 20-bit physical address for the destination. 26

27 8086 Microprocessor Bus Interface Unit (BIU) Architecture Segment Registers Instruction Pointer 16-bit Always points to the next instruction to be executed within the currently executing code segment. Its content is automatically incremented as the execution of the next instruction takes place. 27

28 8086 Microprocessor Execution Unit (EU) Architecture EU Registers Accumulator Register (AX) Consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH contains the high-order byte. 28

29 8086 Microprocessor Execution Unit (EU) Architecture EU Registers Base Register (BX) Consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. This is the only general purpose register whose contents can be used for addressing the 8086 memory. All memory references utilizing this register content for addressing use DS as the default segment register. 29

30 8086 Microprocessor Execution Unit (EU) Architecture EU Registers Counter Register (CX) Consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a counter. 30

31 8086 Microprocessor Execution Unit (EU) Architecture EU Registers Data Register (DX) Consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and DH contains the high-order byte. Used to hold the high 16-bit result (data) in 16 X 16 multiplication or the high 16-bit dividend (data) before a division and the 16-bit reminder after division. 31

32 8086 Microprocessor Execution Unit (EU) Architecture EU Registers Stack Pointer (SP) and Base Pointer (BP) SP and BP are used to access data in the stack segment. SP contents are automatically updated (incremented/ decremented) due to execution of a POP or PUSH instruction. 32

33 8086 Microprocessor EU Registers Architecture Execution Unit (EU) Source Index (SI) and Destination Index (DI) Used in indexed addressing. 33

34 8086 Microprocessor Execution Unit (EU) Flag Register Sign Flag Architecture Auxiliary Carry Flag This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction. Zero Flag Carry Flag This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction. Parity Flag This flag is set, when the result of any computation is negative This flag is set, if the result of the computation or comparison performed by an instruction is zero This flag is set to 1, if the lower byte of the result contains even number of 1 s ; for odd number of 1 s set to zero OF DF IF TF SF ZF AF PF CF Over flow Flag This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow will be set. Direction Flag This is used by string manipulation instructions. If this flag bit is 0, the string is processed beginning from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto incrementing mode. Tarp Flag If this flag is set, the processor enters the single step execution mode by generating internal interrupts after the execution of each instruction Interrupt Flag Causes the 8086 to recognize external mask interrupts; clearing IF disables these interrupts. 34

8086 Microprocessor Architecture 8086 registers categorized into 4 groups 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF DF IF TF SF ZF AF PF CF Sl.No.

35 8086 Microprocessor Architecture 8086 registers categorized into 4 groups OF DF IF TF SF ZF AF PF CF Sl.No. Type Register width Name of register 1 General purpose register 16 bit AX, BX, CX, DX 8 bit AL, AH, BL, BH, CL, CH, DL, DH 2 Pointer register 16 bit SP, BP 3 Index register 16 bit SI, DI 4 Instruction Pointer 16 bit IP 5 Segment register 16 bit CS, DS, SS, ES 6 Flag (PSW) 16 bit Flag register 35

36 Register organization in 80386DX

37 EFLAG REGISTERS IN 80386

38 Virtual mode(vm): set when processor switch into virtual mode. Resume flag (RF): This control flag use with debug registers. It set when debug fault is ignored and next instruction executed normally. Nested task flag (NT): This flag is used in protected mode,when current task called from another task. IOPL: these two bits identify current privilege level in protected mode

39 COPROCESSOR A coprocessor is a computer processor used to supplement the functions of the primary processor (the CPU). Additional operations performed by the coprocessor may be floating point arithmetic, graphical, signal processing, string processing,

40 A special-purpose processing unit that assists the CPU in performing certain types of operations. For example, a math coprocessor (8087) performs mathematical computations, particularly floatingpoint operations. Math coprocessors are also called numeric and floating-point coprocessors. EX. 8087,80387

41 8087 MATH COPROCESSOR USED INTERFACING WITH MATH COPROCESSOR USED INTERFACING WITH

42 REGISTER ORGANIZATION IN i7 PROCESSOR

44 the x86 architecture extended the 32-bit registers into 64-bit registers. An R-prefix identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8-R15) were also introduced in the creation of x However, these extensions are only usable in 64-bit mode

45 Memory address space wide up to 2^64. bytes. Sixteen 64-bit general purpose registers. Six 16-bit segment registers. RFLAG registers 64 bits wide.

46 Features of some i7 registers XMM registers: these 8 registers are used to operate on scalar single precision floating point data.(xmm0- XMM7). MXCSR REGISTER: these 32 bit registers provide status and control bits used in SIMD floating point operations. MMX: These 8 registers are used to perform operations on 64 bit packed integer data.(mmx0- MMX7).

Intel 8086 MICROPROCESSOR ARCHITECTURE

Intel 8086 MICROPROCESSOR ARCHITECTURE 1 Features It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16