POWER9 Announcement. Martin Bušek IBM Server Solution Sales Specialist

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1 POWER9 Announcement Martin Bušek IBM Server Solution Sales Specialist

2 Announce Performance Launch GA 2/13 2/27 3/19 3/20

3 POWER9 is here!!!

4 The new POWER9 processor ~1TB/s 1 st chip with PCIe4 4GHZ 2x Core performance vs x86 BW o chip 7TB/s On chip BW >15 MILES OF WIRE PEAK FREQUENCY 8 BILLION TRANSISTORS 17 LEVELS OF METAL >24B VIAS 1.5x 2x 1.4x performance vs POWER8 more memory vs POWER8 More memory bandwidth vs x86

5 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER Generation Transistor Count (in billions)

6 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9 POWER Generation by CPU lithography in nm

7 Cost ($B) Chip FAB Construction Costs are Rising Chip FAB Construction Cost $6B $10B GlobalFoundries projects that a computer chip manufacturing plant in NY would cost $ billion to build. 2 0 $1B 130 nm 22 nm 14 nm Albany Business Review Semiconductor Manufacturing and Design IBM Corporation, 2016

8 IBM Maains Control of Power and z Systems Stage Description Provider Design Materials Science Manufacturing Create individual chip components and assembling them o synergistic microprocessor solutions The research and development underlying new semiconductor technology innovations Leverage design and materials science to produce chips in commercially sustainable quantities IBM IBM GlobalFoundries IBM Corporation, 2016

9 OpenPOWER Foundation IBM Corporation, 2016

10 Google Confirms POWER9 Processor Data Center Deployment At OpenPOWER Summit 2018 Mahoney explained what Google likes about POWER9: more cores and threads for core Google search more memory bandwidth for RNN machine learning execution faster and "more open" flash NAND sitting on OpenCAPI acceleration bus IBM Corporation, 2016

11 POWER Processor Roadmap POWER5 130 nm GHz POWER5+ 90 nm Dual Core Enhanced Scaling SMT 2 Distributed Switch + Core Parallelism + FP Performance + Memory bandwidth + Virtualization Transistors 276M POWER6 65 nm 3-5GHz POWER6+ 65 nm Dual Core High Frequencies Virtualization + Memory Subsystem + Altivec Instruction Retry Dynamic Energy Mgmt SMT 2+ Protection Keys Transistors 790M POWER7 45 nm 3-4+GHz POWER7+ 32 nm Multi Core (up to 8) On-Chip edram (L3) Power Optimized Cores Mem Subsystem ++ SMT 4 Reliability + VSM & VSX (AltiVec) Protection Keys+ Transistors 1.2B POWER7+ 2.1B POWER8 22 nm 3-4+ GHz Multi Core (up to 12) Double L1 data cache On Chip edram (L3) L4 on Memory ccards Bandwidth +++ SMT 8 Reliability ++ On Chip Power Mgmt PCIe Gen 3 Transistors 4B+ POWER8NV 22 nm POWER9 Enhanced Thread performance Analytics Optimization Extreme Big Data Optimization Next Gen Memory On-chip accelerators Open CAPI BW enhancements Transistors 8B POWER

12

13 POWER9 Processor The core consists primarily of the following six units: instruction fetch unit (IFU), instruction sequencing unit (ISU), loadstore unit (LSU), fixed-po unit (FXU), vector and scalar unit (VSU) and decimal ing po unit (DFU) 13

14 Wikipedia on POWER9 slim core SMT-4 slim Core LSU Load Unit Load from RAM to RAM ALU Arithmetic Logic Integer + compare Instruction Fetch Unit (IFU) Instruction Sequencer Unit (ISU) Super Super L1 Cache Instruction 32KB Data 32KB RAM VSU Vector Scalar Unit Floating po maths + SIMD (Single Instruction Multiple Data) and Vector maths Each of the four CPU core threads gets at least a slice IBM Corporation, 2016

15 Wikipedia on POWER9 fast core SMT-4 slim Core Instruction Fetch Unit (IFU) Instruction Sequencer Unit (ISU) L1 Cache Inst 32KB Data 32KB Super Super RAM SMT-8 Full/Fat/Fast Core Instruction Fetch Unit (IFU) Instruction Sequencer Unit (ISU) Instruction Fetch Unit (IFU) Instruction Sequencer Unit (ISU) L1 Cache Inst 32KB Data 32KB Super Super Super Super L1 Cache Inst 32KB Data 32KB RAM Each of the eight CPU core threads gets at least a slice & up to 8 slices IBM Corporation, 2016

16 Targeted Implementations SMP scalability / Memory subsystem Up to 24 Cores / Chip / socket max of 4 threads per core Linux Ecosystem Optimized Up to 12 Cores / Chip / socket max of 8 threads per core PowerVM Ecosystem Continuity Scale-Out 2 Socket Optimized Robust 2 socket SMP system Direct Memory Attach Up to 8 DDR4 ports Commodity packaging form factor Scale-Up Multi-Socket Optimized Scalable System Topology / Capacity Large multi-socket Buffered Memory Attach 8 Buffered channels 16

17 Two Memory Architectures Scale Out Direct Attach Memory Scale Up Buffered Memory 8 Direct DDR4 Ports 8 Buffered Channels Up to 172 GB/s of bandwidth Up to 230 GB/s of bandwidth Low latency access Extreme capacity up to 8TB / socket Commodity packaging form factor Superior RAS with chip kill and lane sparing (HE) Adaptive 64B / 128B reads Compatible with POWER8 system memory Simplified Design Po Agnostic erface for alternate memory innovations 17

18 Form Factor POWER9 2U / 4U Rack & Tower POWER8 2U / 4U Rack & Tower Comparison CPU Memory I/O 2U - 190W / 225W 4U - 225W / 300W 12 cores (SMT8) or 24 cores (SMT4) 2U - 190W / 225W 4U 225W / 260W 12 cores (SMT8) 74 GB/s - Fabric BW 38.4 GB/s - Fabric BW 4TB 2TB 172 GB/s socket 192 GB/s socket IS DIMMs PCIe GEN3/4 80 GB/s peak BW Max total 26 PCIe Slots (Server + Drawers) CDIMMs PCIe GEN3 (48 lanes) 48GB/s peak BW Max total 31 PCIe Slots (Server + Drawers) 4 CAPI Slots (one x8 and 3 x16) 4 CAPI Slots (x16) 2U 8 SFF Bays 4U 12 / 18 SFF Bays 2U 12 / 8 SFF Bays 4U 12 / 18 SFF Bays 4 ernal NVMe M.2 boot devices Not available RAS 6Gb SAS 2U Single & Dual RAID Write Cache 4U Dual Raid Write Cache 6Gb SAS 2U - Dual RAID Write Cache 4U - Dual RAID Write Cache

19 POWER9 Scale Out family L L S A S A S A H H H H 1,2-socket, 2U 8,10,12 cores/skt 32 IS DIMM slots 4TB memory 4 CAPI 2.0 Slots 1,2-socket, 2U 4, 8,10 cores/skt 32 IS DIMM slots 4TB memory 4 CAPI 2.0 Slots 1-socket, 4U & Tower 4,6,8 cores/skt 16 IS DIMM slots 1TB memory 2 CAPI 2.0 Slots Internal RDX Media 2-socket, 4U 8,10,12 cores/skt 32 IS DIMM slots 4TB memory 4 CAPI 2.0 slots Internal RDX Media 1,2-socket, 2U 4, 8,10 cores/skt 32 IS DIMM slots 4TB memory 4 CAPI 2.0 Slots 2-socket, 4U 8,10,12 cores/skt 32 IS DIMM slots 4TB memory 4 CAPI 2.0 slots Internal RDX Media Linux only PowerVM KVM (GA2) AIX, IBM i, & Linux PowerVM AIX, IBM i, Linux PowerVM AIX, IBM i, Linux PowerVM AIX, IBM i up to 25% Linux PowerVM AIX, IBM i up to 25% Linux PowerVM Technology Leadership Cloud enabled - Embedded virtualization capabilities with PowerVM Up to 4TB in 2 socket - DDR4 Industry Standard memory RDIMMs High Speed 25Gb/s external ports one per socket 2 Internal NVMe Flash boot adapters Embedded Analytics and Algorithms on the chip help run POWER9 at an always optimized frequency 19

20 HANA on POWER9 POWER9 starts with a class leading 4TB 1Q Until SAP certification of HANA on POWER9 expected in early 2Q Production on POWER8 2Q and beyond After SAP certification of HANA on POWER9 POWER8 for capacities larger than 4TB 2H 18 as POWER9 Enterprise Class systems roll out POWER9 H models for Linux-minded clients 2H 18 (Cont.) H models will be preferred for HANA for more aggressive pricing and configurations Early POC on POWER9 POWER9 H models for Linux-minded clients S922/S924 if clients needs more than 25% AIX/IBM i core activations S922/S924 if clients needs more than 25% AIX/IBM i core activations POWER9 H980/H950 for larger than 4TB using ECOD for AIX/ IBM i Elastic Capacity on Demand offered on H980 and H950 will give full flexibility to deploy AIX/ IBM i on H models (Linux) 20

21 AIX Support Roadmap P9 Enablement SP

22 IBM i Support Roadmap

23 IBM Operating System Plans for POWER9 Power Systems SP3 AIX 5.3 AIX 6.1 AIX 7.1 AIX 7.2 IBM i 7.1 IBM i 7.2 IBM i 7.3 POWER9 POWER8 23

24 Thank you! 24

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