The RM9150 and the Fast Device Bus High Speed Interconnect

Size: px

Start display at page:

Download "The RM9150 and the Fast Device Bus High Speed Interconnect"

Darcy Osborne
5 years ago
Views:

1 The RM9150 and the Fast Device High Speed Interconnect John R. Kinsel Principal Engineer -sierra.com 1 August 2004 Agenda CPU-based SOC Design Challenges Fast Device (FDB) Overview Generic Device FDB Block Diagram Architectural Advantages Summary 2 August 2004

2 Typical CPU-based SOC Building Blocks CPU Core Needs low latency Parallelism Interconnect DDR Memory Local Hyper Needs high throughput System bus architecture is becoming increasingly important CPU frequency increase must be matched by bus and memory speeds 3 August 2004 SoC Design Issues 1 GHz CPU Core 66MHz Multiple clock domains needed Interconnect DDR Memory 200MHz Local Hyper 50 MHz 600 MHz 1 Gbps x2 1 Gbps x2 (Tx / Rx) (Tx / Rx) Custom bus interface to each peripheral - Little design re-use Performance scalability issues 4 August 2004

3 Typical Bandwidth of Various Blocks CPU Core Bandwidth 1.6 GBytes/s Interconnect 0.25 GB/s DDR Memory 2.6 GB/s Local Hyper 2.4 GB/s 0.25 GB/s 0.25 GB/s Bandwidth 1.6 GBytes/s < 0.25 GB/s () 2.6 GB/s (DDR) 2.4 GB/s (HT) 0.25 GB/s (GE) 0.25 GB/s (GE) 5.75 GB/s peripheral bandwidth Typical standard buses can t keep up with memory controller and other high-bandwidth peripherals 5 August 2004 Fast Device / Generic Device port port port port port Request Request Core (128-bits) port port port port Physical Address Map Common design interface for all peripherals interface specification available to PMC customers 6 August 2004

4 Fast Device Features port port port port port Request Request Core (128-bits) port port port port Physical Address Map arbitration logic and physical address map Modular design, ports can be easily added and subtracted (2-12) 7 August 2004 Fast Device Features (cont.) port port port port port Request Request Core (128-bits) port port port port Physical Address Map 128-bits, multiplexed address and data Separate grant signal, addr./data grant per port 400 MHz 500 MHz multiple master, shared on-chip bus 3-bit credit release bus, one per port connected from each port to the central arbiter 8 August 2004

5 Operation / Advantages Employs a two-stage arbiter - Request : Round robin priority - Second stage: Choose next owner of A/D bus based on request priority / target transaction resource availability - Both arbiters are pipelined, selecting a new owner every cycle The is for efficient scheduling of main bus usage - Main bus is never granted unless the target can accept the transaction, therefore no not acknowledges and no retries The guarantees fair access to high-contention targets port port port port port Request Request Core (128-bits) port port port port Physical Address Map 9 August 2004 First Device Based on the FDB: RM9150 DDRI/2 Local Hyper 128-bit 64-bit 64-bit 64-bit DMA Fast Device (FDB) 64-bit 64-bit 64-bit 64-bit E9000 On-chip INT XDMA Ctrler CPU Mem. Packet FIFO GE Port 0 GE Port 1 GE Subsystem Proc. Int. DUART SCMB SCMB SCMB 2-wire MDIO/ MDC FDB is implemented using a single core clock domain 64-bit Each port contains a fixed number of buffers to accept a fixed number of transactions Number of buffers optimized to meet each device s specific performance requirements Built-in re- synchronization logic to support different frequency modes - Asynchronous - Semi-synchronous - Full synchronous 128-bit to FDB interface for DDR1/2 memory controller for optimum bandwidth 10 August 2004

6 FDB/ Methodology Greatly Reduces Verification Effort Only need to design new Intellectual Property (IP) blocks with interface (or modify existing IP to support ) Once this IP with interface has been verified, then this ensures that the IP block can communicate with the FDB and all devices connected through to the FDB Without / FDB, would need to design a custom interface to each IP block and verify that it can communicate with the system interconnect (for each peripheral device in the SOC) Solves an order (n 2 ) verification problem by reducing it to an order (n) effort 11 August 2004 RM9150 Feature Summary First PMC-Sierra SOC to implement the FDB/ E9000 processor (<500 MHz to 1GHz capability) - 64-bit, dual-issue, superscalar, 7-stage pipeline - 16KB L1 caches / 256KB L2 cache (parity, ECC) FDB Trace and Performance Monitor 8-bit 600 MHz DDR Hyper v1.03 Two 32-bit buses, 66 MHz, v2.3 Dual 10/100/1000 MII/GMII/TBI 2BI/MDIO EJTAG Interrupts Clocks RM9150 Local DUART GPIO 167MHz/ 200 MHz 64-bit DDRI/II SDRAM - Up to 4GB of memory DDRI/II 72- bit SDRAM Dual 32- bit 8-bit Hyper Two 10/100/1000 s (802.3), TBI, GMII, MII 4-channel DMA controller 896 BGA package 0.13um TSMC process Local controller to external ROM, Flash, Compact Flash, PCMCIA, USB 2.0 devices Serial Communications Master Block - DUART, 2-wire interfaces, MDIO/MDC, 64 GPIO 12 August 2004

7 PMC s Solution: New Design Methodology - Performance flexibility & quick-turn SOC designs High End RM9000x2GL Non-Blocking Crossbar Switch Mid Range RM9150 Fast Device Low End Future Lite Fast Device 13 August 2004 Fast Device / Generic Device Architectural Advantages allows each peripheral to interface to FDB fully synchronously, semi-synchronously, or totally asynchronously, essentially eliminating global clocking issues Standard interface allows development of re-usable IP blocks, ability to use different future bus interconnects allows replacement of the interconnect behind it without redesigning the peripheral devices -> scalability Allows customers to integrate their IP or leverage PMC s IP to quickly design complex SOC s at various price/performance points Greatly reduces device verification effort (factor of n) for fast time-tomarket 14 August 2004

8 Summary Innovative Fast Device / bus architecture - Tuned for optimal performance (latency, bandwidth to critical peripherals) - High utilization due to efficient arbitration - Enables easy design re-use (common interface) E9000 CPU and robust set of RM9150 peripherals address multiple market segments - Networking, Storage, Industrial Control, and High-end Printer and Consumer First instance of PMC s platform-based high-performance, highly integrated SOCs using the FDB 15 August 2004 Thinking You Can Build On 16 August 2004

The CoreConnect Bus Architecture

The CoreConnect Bus Architecture Recent advances in silicon densities now allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripherals formerly attached