CSE A215 Assembly Language Programming for Engineers
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1 CSE A215 Assembly Language Programming for Engineers Lecture 6 MIPS vs. ARM and Number Representation Part-2 (COD Chapter 3) September 20, 2012 Sam Siewert
2 Comparison of MIPS32 and ARM General Purpose Register Files, Instructions and Addressing Sam Siewert 2
3 A Brief History and Scope Both MIPS and ARM Now have 32-bit and 64-bit ISAs ARM Has Rapidly Growing Market Share and Announced 64-bit ISA Both Compete with Intel s 32-bit Atom Architecture PowerPC 32-bit Embedded No Longer Updated IBM & Motorola (AMCC Applied Micro Circuits Corporation) ARM ISA MIPS ISA x86 ISA ARM v1 ARM v2 ARM v3 ARM v4 MIPS I MIPS II MIPS III MIPS IV MIPS V i ARM v5te XSC ARM v6 ARM v7 (NVIDIA Tegra3) ARM v8 64-bit MIPS32&64 MIPS32 24K MIPS64 Cavium Octeon XSC Atom * Dates are approximate based on observed/documented use in products Sam Siewert 3
4 MIPS Register File bit General Purpose Registers with Conventions Summarized on Ref. Card and page 121 in COD Register Fill and Spill As Needed for Execution Context Sam Siewert 4
5 ARM Register File ARM bit GP Registers Banked by Processor Mode System & User normal mode FIQ fast interrupt and exception handling IRQ normal interrupt handling Sam Siewert 5
6 ARM vs MIPS ISA Section 2.16 in COD Highly Recommend Knowledge of Both ARM has only 16 Rd, Rn Registers for Destination and Source Shift Operations Done by Barrel Shifter on ALU Operand2 Input Conditional Execution of All Instruction Formats Processor Modes Banked Registers for Fast Context Switch (e.g. Interrupt to Normal Execution) Block Data Transfer 1 to 16 Register Spill/Fill No DIV instruction, must be done in Software Sam Siewert 6
7 ARM9 v5te ISA 5-Stage* Both Are Pipelined MIPS 5-Stage New Features on both Resulting in New Hazards (and New Stages) ARM Has Evloved from 3 Stage (IF, ID, Execute) on ARM7 To 5 Stage on ARM9 As Shown Above To 8 Stage on ARM11 (Fetch-1, Fetch-2, Decode, Register Read, Shift, Data-1, Data-2, Write-Back) * The ARM Architecture, Leonid Ryzhyk, June 5, Sam Siewert 7
8 Our Approach Learning ASM for any Architecture Somewhat Universal ASM Mneumonics (Opcodes) and Operands Register Files Common ISA Principals for Stored Program Von Neumann Architectdure MIPS32, Simple, Instructive, Available with QtSPIM Simulator Can Study on Paper Only Simple ISA instruction format and register file Or Use QtSPIM for Exercises (9.1.7 for Windows from COD) on Resources in BB for Reference ARM v7 Widely used and available low-cost educational hardware Beagle xm, Raspberry Pi, Panda, etc. ($50 up to $200) Using Real Hardware Provides Performance and Real World Experience with Linux QEMU ARM emulator for Linux available wiki.qemu.org/download Emulators Often Used During Pre-Silicon Concurrent Development of Software with Hardware Sam Siewert 8
9 Number Representation and Operations Integer Multiplication & Division And Floating Point (IEEE 754) Sam Siewert 9
10 The Slow Way Binary Multiplication 3 Clocks for Each Bit Plus Initialization and Write-Back 100 cycles Emulates Hand Method for Multiplication used in Base-10 in Base-2 COD P. 234, Figure 3.7 Results Can be Twice # of Bits E.g. Octal 4 8 x 7 8 = 34 8, is Binary 100 x 111 = 011_ (multiplicand) x 100 (multiplier) (step #1, first digit, 0 x 111) 000 (step #2, shift left, second digit, 0 x 111) 111 (step #3, shift left, third digit, 1 x 111) (step #4, sum all columns, implied 0 in blanks) Sam Siewert 10
11 Slow Automation for Multiply Repeat for all Bits with Result=0x to Start Series of 3 clocks to: 1. Sum: Result = Result + Mcand 2. Shift Left Mcand 3. Shift Right Mplier Iteration Operation Mplier Mcand Result 0 Initial values LS bit of Mplier 0, No-op SL Mcand SR Mplier LS bit of Mplier 0, No-op SL Mcand SR Mplier LS bit of Mplier 1, Result=Result+Mcand Bold indicates register value changed Sam Siewert 11
12 Faster Automation Each Iteration For Different Portions of a Word Can Be Executed in Parallel Such that log 2 (word_size) clocks are needed for all iterations E.g. for 32-bit, 5-layer ALU Stack using 31 parallel ALUs Or, for Simple Hex Example, 4-bit, a 2-layer ALU stack using 3 parallel ALUs Hex 4 16 x 7 16 = 1C 16, is Binary 0100 x 0111 = 0001_1100 Iteration Operation Mplier Mcand Result 0 Initial values LS bit of Mplier 0, No-op SL Mcand SR Mplier LS bit of Mplier 0, No-op SL Mcand SR Mplier LS bit of Mplier 1, Result=Result+Mcand SL Mcand SR Mplier LS bit of Mplier 0, No-op Bold indicates register value changed Sam Siewert 12
13 2-Layer Fast Multiplier for 4-bit Hex Execute Mplier RS, test for 1 and Add in Parallel (4 16 x 7 16 = 1C 16 ) Sum Each Shifted Product in Second Stage Produces 8-bit Hex Result in 2-Layer ALU Stack Can Scale to 32-bit Inputs and 64-bit Result with 5 Layers 0 & & & & 0111 Mplier3 & Mcand 0000 Mplier2 & Mcand 0111 Mplier1 & Mcand 0000 Mplier0 & Mcand bits 4 bits bits R7 R6 R5 R4 R3 R2 R1 R Sam Siewert 13
14 Final Notes on Multiply Signed Multiply Simple Tests MS bit of Each Operand Save Sign Bits from Each Operand Convert Each Operand to Unsigned and Multiply as Before Assign New Sign Based on Those Saved (Negate if Different) Overflow is Expected into High Word Register Non-zero High Word Register Indicates Overflow Up to Software to Decide How to Handle E.g. type promotion of result to Double Word? Multiply is More Common than Divide ARM Has NO Divide, Just Multiply Divide Requires Function, MIPS Does Include Divide Operator Sam Siewert 14
15 Binary Division Dividend = (Quotient x Divisor) + Remainder E.g. 28 = (9 x 3) + 1, or 0x1C = (0x09 x 0x03) + 0x01 Quotient = Dividend / Divisor Remainder = Dividend modulo Divisor 0 Divisor and Quotient Overflow Errors Possible 1001 (quotient) (subtract or add 2 s comp) (subtract or add 2 s comp) (remainder when < divisor) Sam Siewert 15
16 Hard to Speed-up SRT Sweeney, Robertson, and Tocher Caused Pentium Bug Division Hardware Sam Siewert 16
17 Floating Point 32 Bit float MS bit is the Sign Bit (-1) S Exponent Bits in MIPS Fraction (Mantissa) Bits 22 0 in MIPS Exponent is Biased (by 127) to Be Monotonically Decreasing for Sorting Float = (-1) S x F x 2 E Addition or Subtraction: Shift for Common Exponent, Add, Normalize Multiplication: Add Exponents, Subtract Bias, Multiply Mantissas, Normalize Division: Subtract Exponents, Subtract Bias, Divide Mantissas, Normalize Sam Siewert 17
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