Lecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
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1 Lecture Topics Today: Single-Cycle Processors (P&H ) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1
2 Exam #1 Wednesday, 2/15 (3:00-4:20 PM) 101 Biochemistry Building 80 minutes, 18% of course grade Study suggestions on course website 3 ISA Implementations The ISA for a particular processor defines the features of that machine: instructions, registers, etc The fetch-execute cycle governs the processor: Fetch current instruction Decode and execute it Update PC to point to next instruction 4 2
3 MIPS Fetch-Execute Cycle Fetch Phase: MEM[ PC ] ==> IR PC + 4 ==> PC Execute Phase: decode IR take appropriate action 5 Single-Cycle Implementation Each instruction completes in one clock cycle (fetch and execute in same cycle) Length of clock period determined by worst case (instruction category with longest path through circuits) 6 3
4 Fetch Phase PC contains address of current instruction PC serves as input to Instruction Memory (Instruction Cache) Instruction Memory returns instruction Address of next sequential instruction is at PC+4 7 Execute Phase Decode instruction extract operation code info extract register numbers, immediate value Execute instruction generate control signals use circuits to take the correct actions for this particular instruction 8 4
5 P&H MIPS Implementation Patterson and Hennessy describe a simplified version of the MIPS in chapter 4 Only a small subset of instructions: ADD, SUB, AND, OR, SLT LW, SW BEQ, J We need to consider a richer set of instructions 9 MIPS Instruction Categories Data manipulation R-format (both operands in registers) I-format (one immediate value Data movement Control transfer R-format (jump register) I-format (branch) J-format (jump) 10 5
6 R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result 11 Load and Store Instructions Read register operands Calculate address using ALU: R[rs] + 16-bit offset (sign extended) Load: Read memory and update register Store: Write register value to memory 12 6
7 R-Format/LW/SW Datapath 13 Branch Instructions Read register operands Compare operands using ALU: subtract and check Zero output Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 (from fetch phase) 14 7
8 Branch Instructions Just re-routes wires Sign-bit wire replicated 15 Combining the Elements Single-cycle implementation: one instruction in one clock cycle Each datapath element can only do one function at a time Must have separate instruction and data memories (Harvard architecture) Use multiplexers where alternate data sources are used for different instructions 16 8
9 R-Format/LW/SW/BEQ Datapath 17 ALU Control Unit ALU used by most instructions Load and Store: add to compute address Branch: subtract to compare operands R-type: operation depends on funct field ALU operation Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR 18 9
10 ALU Control Unit Generate ALU using combinational logic (ALU control unit) inputs: ALUop (derived from IR), IR[5:0] output: ALU operation ALU operation Function AND 6 ALU Control OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR 19 ALU Control Unit ALUOp (2 bits): derived from instruction funct (6 bits): IR[5:0] ALU operation (4 bits): control signal for ALU Instruct ALUOp Operation funct ALU function ALU operation lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add add 0010 subtract subtract 0110 AND AND 0000 OR OR 0001 set-on-less-than set-on-less-than
11 Main Control Unit Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read read, except for load write for R-type and load sign-extend 21 Datapath With Control 22 11
12 R-Type Instruction 23 Load Instruction 24 12
13 Branch-on-Equal Instruction 25 Implementing Jumps Jump address 31:26 25:0 Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 Need control signal decoded from opcode 26 13
14 Datapath With Jumps Added 27 Performance Issues Longest delay determines clock period Critical path: load instruction instruction memory register file ALU data memory register file Not feasible to vary clock period for different instructions Violates design principle (make the common case fast) 28 14
15 Single-Cycle Pros and Cons Simple and easy to understand Uses the clock cycle inefficiently: the clock cycle must accommodate the slowest instruction Clk Cycle 1 Cycle 2 lw sw Waste 29 Multi-Cycle Approach Let an instruction take more than one clock cycle to complete Break up instructions into steps where each step takes one clock cycle Clock period is much shorter Not every instruction takes the same number of clock cycles 30 15
16 Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 LW IFetch Dec Exec Mem WB IFetch: Instruction Fetch and Update PC Dec: Instruction Decode, Register Read, Sign Extend Offset Exec: Execute R-type; Calculate Memory Address; Branch Comparison; Branch and Jump Completion Mem: Memory Read; Memory Write Completion; R-type Completion (RegFile write) WB: Memory Read Completion (RegFile write) INSTRUCTIONS TAKE FROM 3-5 CYCLES! 31 Multi-Cycle Pros and Cons Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Uses the clock cycle efficiently the clock cycle accommodates the slowest instruction step Requires additional internal state registers, more MUXes, and more complicated (FSM) control 32 16
17 Single Cycle vs. Multi-Cycle Timing Single Cycle Implementation: Clk Cycle 1 Cycle 2 lw sw Waste multicycle clock slower than 1/5 th of Multiple Cycle Implementation: single cycle clock due to state register overhead Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch 33 17
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