Samsung S3C4510B. Hsung-Pin Chang Department of Computer Science National Chung Hsing University

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1 Samsung S3C4510B Hsung-Pin Chang Department of Computer Science National Chung Hsing University

2 S3C4510B A 16/32-bit RISC microcontroller is a cost-effective, highperformance microcontroller 16/32-bit ARM7TDMI 8K-byte unified cache/sram I 2 C Serial Interface Ethernet controller HDLC (High-Level Data Link Control ) For X.25 communication standard GDMA 2-channel General DMA for memory-to-memory, memory-to-uart, UART-tomemory data transfers without CPU intervention UART Timers Programmable I/O ports Interrupt controller

3 S3C4510B Block Diagram

4 Pin Assignment Diagram

5 Signal Descriptions

6 CPU Core 32-bit ARM7TDMI microprocessor Developed by Advanced RISC Machines, Ltd. (ARM) Can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions

7 Instruction Set A standard 32-bit ARM instruction set and a 16-bit THUMB instruction set. The 32-bit ARM instruction set is divided into four broad classes Four types of branch instructions Control program execution flow Control instruction privilege levels, and Switching between an ARM code and a THUMB code Three types of data processing instructions Use the on-chip ALU, barrel shifter, and multiplier to perform highspeed data operations in a bank of 31 registers Three types of load and store instructions Control data transfer between memory locations and the registers Three types of co-processor instructions

8 Operating States ARM state Executing 32-bit, word-aligned, ARM instructions THUMB state Executing 16-bit, half-word aligned THUMB instructions These states can be switched by software or by exception processing

9 Operating Modes User mode: a normal program execution state FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel processing IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling Supervisor mode: a protected mode for the operating system Abort mode: entered when a data or instruction pre-fetch is aborted System mode: a privileged user mode for the operating system Undefined mode: entered when an undefined instruction is executed

10 Registers S3C4510B CPU core has a total of 37 registers 31 general-purpose 32-bit registers, 6 status registers. Not all of these registers are always available

11 Exceptions An exception arises when the normal flow of program execution is interrupted The processor state just prior to handling the exception must be preserved The program flow can be resumed when the exception routine is completed To process exceptions, the S3C4510B uses the banked core registers to save the current state The old PC value are copied into the R14 (LR) register The CPSR contents are copied into the SPSR registers.

12 Special Registers

13 Special Registers (Cont.)

14 Special Registers (Cont.)

15 Special Registers (Cont.)

16 System Memory Map The size and location of each memory bank is determined by the register setting Bank base pointer ~ Bank end pointer S3C4510B allows up to Six ROM/SRAM/Flash banks Four DRAM/SDRAM banks Four external I/O banks A special register mapping area

17 System Memory Map

18 Memory Map at Power-On/Reset All bank address pointer registers are initialized to their default value All bank pointer except for the next pointer of ROM bank 0 are set to zero Base pointer of ROM bank 0 = 0x000 Next pointer of ROM bank 0 = 0x200 ROM bank 0 as a 32-Mbyte space starting from memory 0x To hold the boot code or boot loader

19 Memory Map at Power-On/Reset (Cont.)

20 Determine the Memory Map Determine special register area Set SYSCFG register Determine ROM/SRAM/FLASH bank area Set ROMCON0~ROMCON5 registers Determine DRAM bank area Set DRAMCON0 ~ DRAMCON3 register Determine External I/O bank Set REFEXTCON register

21 Determine the Memory Map (Cont.) Four external I/O banks are defined in a continuous address space The size of each external I/O bank is fixed at 16 Kbytes Programmer can only set the base pointer for external I/O bank 0 (REFEXTCON register) The start address of external I/O bank 1 = external I/O bank K The start address of external I/O bank 2 = external I/O bank K The start address of external I/O bank 3 = external I/O bank K

22 Other Issues System Manager Unified Instruction/data cache I 2 C Bus Controller Ethernet Controller HDLC Controller DMA Controller Serial I/O (UART) 32-Bit Timer I/O Ports Interrupt Controller

23 Reference Samsung S3C4510B User s Manual r/systemlsi/networks/personalntassp/comm unicationprocessor/s3c4510b/s3c4510b.htm

Chapter 4. Enhancing ARM7 architecture by embedding RTOS

Chapter 4. Enhancing ARM7 architecture by embedding RTOS Chapter 4 Enhancing ARM7 architecture by embedding RTOS 4.1 ARM7 architecture 4.2 ARM7TDMI processor core 4.3 Embedding RTOS on ARM7TDMI architecture 4.4 Block diagram of the Design 4.5 Hardware Design