# CPEG300 Embedded System Design. Lecture 3 Memory

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1 CPEG300 Embedded System Design Lecture 3 Memory Hamad Bin Khalifa University, Spring 2018

2 Review Von Neumann vs. Harvard architecture? System on Board, system on chip? Generic Hardware Architecture of a Microcontroller? 8051 history, block diagram and on-chip resources 8-bit CPU 4K Internal RoM, 128B RAM, 64K memory extension (ROM, RAM) 16-bit counter x2, Interrupts x5 8-bit I/O ports x4, UART x supply, reset and system clock? Clock period, machine cycle (state, beat), instruction cycle? Instruction fetch stage and the instruction execution stage? 2

3 Memory Capacity The number of bits that a semiconductor memory chip can store is called chip capacity. It can be in units of Kbits (kilobits), Mbits (megabits), and so on. This must be distinguished from the storage capacity of computer systems While the memory capacity of a memory IC chip is always given bits, the memory capacity of a computer system is given in bytes o 16M memory chip 16 megabits o A computer comes with 16M memory 16 megabytes Memory chips are organized into a number of locations within the IC Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is designed internally o The number of locations within a memory IC depends on the address pins (e.g. 2 X locations, X is the number of address pins) o The number of bits that each location can hold is always equal to the number of data pins (e.g. Y) o The entire chip will contain 2 X * Y bits 3

4 Example 1. A given memory chip has 12 address pins and 4 data pins. Find: (a) The organization, and (b) the capacity. Solution: (a) This memory chip has 4096 locations (2 12 = 4096), and each location can hold 4 bits of data. This gives an organization of , often represented as 4K 4. (b) The capacity is equal to 16K bits since there is a total of 4K locations and each location can hold 4 bits of data. 2. A 512K memory chip has 8 pins for data. Find: (a) The organization, and (b) the number of address pins for this memory chip. Solution: (a) A memory chip with 8 data pins means that each location within the chip can hold 8 bits of data. To find the number of locations within this memory chip, divide the capacity by the number of data pins. 512K/8 = 64K; therefore, the organization for this memory chip is 64K 8 (b) The chip has 16 address lines since 2 16 = 64K 4

5 80C51 Block Diagram Overall system view - 8-bit CPU - 4K Internal RoM - 128B RAM (Maximum 256B) - 64K maximum memory extension (ROM, RAM) 5

6 8051 MCU Memory Structure 4-types of memory in 8051 MCU Program memory Internal (RoM, typically 0 ~ 4K) o ROM PROM EPROM E2PROM Flash, etc. External (RoM) o ROM PROM EPROM E2PROM Flash, etc. ROM is a type of memory that does not lose its contents when the power is turned off, also called nonvolatile memory! Data Memory Internal (RAM, typically 256B) o SRAM NVRAM DRAM, etc. External (RAM) o SRAM NVRAM DRAM, etc. RAM memory is called volatile memory since cutting off the power to the IC will result in the loss of data. RAM is also referred to as RAWM (read and write memory). 6

7 Memory Structure 8051 chip RAM ROM FFFFh 0000h External DATA Memory (up to 64KB) RAM SFR I-RAM Program FFFFh 0000h External CODE Memory (up to 64KB) ROM 7

8 Program Memory Space (ROM) Since the PC (program counter) of the 8031/51 is 16-bit, it is capable of accessing up to 2 16 = 64K bytes of program code In case of 4KB of Internal ROM, the address space is 0000H to 0FFFH For maximum 64K external ROM, the address space is 0000H to FFFFH External ROM access is controlled by EA\ pin If there s no internal ROM, EA\ should be tied LOW EA\ is V DD EA\ is GND EA External ROM 64K FFFFh EA External ROM 64K FFFFh 1000h 0000h 0FFFh 0FFFh Internal ROM 4K Internal ROM 4K 0000h 0000h 8

9 Data Memory Space (RAM) The 8051 s on-chip memory consists of 256 memory bytes organized as follows: Lower128 bytes: o 00h to 1Fh Register Banks o 20h to 2Fh Bit Addressable RAM o 30 to 7Fh General Purpose RAM, byte addressable Higher128 bytes: o 80h to FFh Special Function Registers FFh 80h 7Fh 00h Data Memory Special function registers (SFRs) Internal RAM 7Fh 30h 2Fh 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h 80 general purpose registers 16 bit-addressable registers Regs (Bank 3) Regs (Bank 2) Regs (Bank 1) Regs (Bank 0) Register Bank0 07h R7 06h R6 05h R5 04h R4 03h R3 02h R2 01h R1 00h R0 9

10 Bit-addressable Registers Bit Addressable RAM: 20h to 2Fh: 128 bits in total numbered 00h to 7Fh. Any one variable can have a value 0 or 1. A bit variable can be set with a command such as SETB and cleared with a command such as CLR. o SETB 25h ;sets the bit 25h (becomes 1) 7Fh 30h 2Fh 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h o CLR 25h ;clears bit 25h (becomes 0) 80 general purpose registers 16 bit-addressable registers Regs (Bank 3) Regs (Bank 2) Regs (Bank 1) Regs (Bank 0) 7F 7E 7D 7C 7B 7A F 6E 6D 6C 6B 6A F 5E 5D 5C 5B 5A F 4E 4D 4C 4B 4A F 3E 3D 3C 3B 3A F 2E 2D 2C 2B 2A F 1E 1D 1C 1B 1A F 0E 0D 0C 0B 0A

11 Stack Stack is a section of RAM to store information (data or address) temporarily (for interrupt, field, temp. data protection) Last in, first out (LIFO). There is a register inside the CPU to point to it, called SP (stack pointer) register. SP is 8 bits wide (can take values of 00 to FFH), points to the top of the stack. SP = 07h after power-up or reset à RAM location 08h is the first location used for the stack. o MOV SP, #2Fh ;initialize the stack PUSH: storing of a data in the stack POP: pulling the contents off the stack back into a CPU register. In other words, a register is pushed onto the stack to save it and popped off the stack to retrieve it. The job of the SP is very critical when push and pop actions are performed. 11

12 Stack Operation Operation example: PUSH 05h; //firstly SP=SP+1, then store 05h in the address pointed by SP; POP A; //firstly retrieve the data pointed by SP and assign it to A, then SP=SP-1; LIFO Stack operation 12

13 SFR Registers SFRs provide control and data exchange with the microcontroller s resources and peripherals; The SFR registers are located within the Internal Memory in the address range 80h to FFh. Not all locations within this range are defined. Each SFR has a very specific function. Each SFR has an address and a name which reflects the purpose of the SFR. Although 128 byes of the SFR address space is defined only 21 SFR registers are defined in the standard Undefined SFR addresses should not be accessed as this might lead to some unpredictable results. Note some of the SFR registers are bit addressable. SFRs are accessed just like normal Internal RAM locations. Registers which have their byte addresses ending with 0H or 8H are byte- as well as bit- addressable. 13

14 SFR Register Table Special Function Register Symbol Name Byte Address TH1 Timer 1 High 8b 8Dh TH0 Timer 1 Low 8b 8Ch TL1 Timer 0 High 8b 8Bh TL0 Timer 0 Low 8b 8Ah TMOD Timer Mode Control 89h *TCON Timer/Counter Control 88h PCON Power Control 87h DPH Data Pointer High 8b 83h DPL Data Pointer Low 8b 82h SP Stack Pointer 81h *P0 Port 0 80h Special Function Register Symbol Name Byte Address *B B Register F0h *A or ACC Accumulator E0h *PSW Program Status Word D0h *IP Interrupt Priority B8h *Port 3 (P3) Port 3 B0h *IE Interrupt Enable A8h *Port 2 (P2) Port 2 A0h SBUF Serial Port Data Buffer 99h *SCON Serial Port Control 98h *Port 1 (P1) Port 1 90h * indicates the SFR registers which are bit addressable 14

16 Immediate Addressing Immediate addressing: the operand (which immediately follows the instruction code) is the data value to be used. For example: MOV A, #99d ;moves 99 (decimal) to A (accumulator) A E0h 99d The # symbol tells the assembler that immediate addressing mode is used. MOV A,#25H ;load 25H into A MOV R4,#62 ;load 62 into R4 MOV B,#40H ;load 40H into B MOV DPTR,#4521H ;DPTR=4512H MOV DPL,#21H ;This is the same MOV DPH,#45H ;as above MOV DPTR,#68975 ;illegal!! Value > (FFFFH) 16

17 Register Addressing Register addressing: one of the eight general-registers, R0 to R7, A, B, CY, DPTR in SFR can be specified as the instruction operand. For example: ADD A, R5 ;adds register R5 to A (accumulator) A R5 E0h h The source and destination registers must match in size: MOV DPTR,A will give an error; The movement of data between Rn registers is not allowed: MOV R4,R7 is invalid; MOV A,R0 ;copy contents of R0 into A MOV R2,A ;copy contents of A into R2 ADD A,R5 ;add contents of R5 to A ADD A,R7 ;add contents of R7 to A MOV R6,A ;save accumulator in R6 17

18 Direct Addressing Direct addressing: the data value is obtained directly from the memory location specified in the operand. For example: MOV A, 47h ;read the data from Internal RAM address 47h and stores it in A E0h A Internal RAM 48h 47h 46h Direct addressing can be used to access Internal RAM, including the SFR registers, where SFR can be addressed by the names or addresses; Only direct addressing mode is allowed for pushing or popping the stack: PUSH A is invalid; Pushing the accumulator onto the stack must be coded as PUSH 0E0H MOV R0,40H ;save content of 40H in R0 MOV 56H,A ;save content of A in 56H MOV 0E0H,#55H ;is the same as MOV A,#55h ;load 55H into A 18

19 Register Indirect Addressing Register Indirect Addressing: For example: MOV A Internal RAM 52h R0 E0h 54h 54h 00h 53h symbol indicates indirect addressing mode is used. R0 contains a value, for example 54h, which is to be used as the address of the internal RAM location, which contains the operand data. Indirect addressing refers to Internal RAM only and cannot be used to refer to SFR registers. Note, only R0 or R1 can be used as register data pointers for indirect addressing. The 8052 (as opposed to the 8051) has an additional 128 bytes of internal RAM. These 128 bytes of RAM can be accessed only using indirect addressing. 19

23 Bit Addressing To avoid confusion regarding the addresses 00 7FH The 128 bytes of RAM have the byte addresses of 00 7FH can be accessed in byte size using various addressing modes o Direct and register-indirect The 16 bytes of RAM locations 20 2FH have bit address of 00 7FH o We can use only the single-bit instructions and these instructions use only direct addressing mode The BIT directive is a widely used directive to assign the bitaddressable I/O and RAM locations Allow a program to assign the I/O or RAM bit at the beginning of the program, making it easier to modify them 23

25 Practice Read the code: MOV R0, #30h MOV ADD A, R0 A ;immediate ;indirect ;register ;indirect 25

26 Appendix PROM (Programmable ROM) PROM refers to the kind of ROM that the user can burn information into PROM is a user-programmable memory For every bit of the PROM, there exists a fuse If the information burned into PROM is wrong, that PROM must be discarded since its internal fuses are blown permanently PROM is also referred to as OTP (one-time programmable) Programming ROM, also called burning ROM, requires special equipment called a ROM burner or ROM programmer 26

27 Appendix EPROM (Erasable Programmable ROM) EPROM was invented to allow making changes in the contents of PROM after it is burned In EPROM, one can program the memory chip and erase it thousands of times A widely used EPROM is called UVEPROM UV stands for ultra-violet, The only problem with UV-EPROM is that erasing its contents can take up to 20 minutes All UV-EPROM chips have a window that is used to shine ultraviolet (UV) radiation to erase its contents. There is an EPROM programmer (burner), and there is also separate EPROM erasure equipment. The major disadvantage of UV-EPROM, is that it cannot be programmed while in the system board. To program a UV-EPROM chip, the following steps must be taken: Its contents must be erased o To erase a chip, it is removed from its socket on the system board and placed in EPROM erasure equipment to expose it to UV radiation for minutes Program the chip o To program a UV-EPROM chip, place it in the ROM burner o To burn code or data into EPROM, the ROM burner uses 12.5 volts, V pp in the UV-EPROM data sheet or higher, depending on the EPROM type o Place the chip back into its system board socket 27

28 Appendix EEPROM (Electrically Erasable Programmable ROM) EEPROM has several advantage over EPROM Its method of erasure is electrical and therefore instant, as opposed to the 20-minute erasure time required for UVEPROM One can select which byte to be erased, in contrast to UV- EPROM, in which the entire contents of ROM are erased One can program and erase its contents while it is still in the system board o EEPROM does not require an external erasure and programming device o The designer incorporate into the system board the circuitry to program the EEPROM 28

29 Appendix Flash Memory EPROM Flash EPROM has become a popular user-programmable memory chip since the early 1990s The process of erasure of the entire contents takes less than a second, or might say in a flash o The erasure method is electrical o It is commonly called flash memory The major difference between EEPROM and flash memory is o Flash memory s contents are erased, then the entire device is erased There are some flash memories are recently made so that the erasure can be done block by block o One can erase a desired section or byte on EEPROM It is believed that flash memory will replace part of the hard disk as a mass storage medium The flash memory can be programmed while it is in its socket on the system board o Widely used as a way to upgrade PC BIOS ROM Flash memory is semiconductor memory with access time in the range of 100 ns compared with disk access time in the range of tens of milliseconds Flash memory s program/erase cycles must become infinite, like hard disks o Program/erase cycle refers to the number of times that a chip can be erased and programmed before it becomes unusable o The program/erase cycle is 100,000 for flash and EEPROM, 1000 for UV- EPROM 29

30 Appendix Mask ROM Mask ROM refers to a kind of ROM in which the contents are programmed by the IC manufacturer, not user programmable The terminology mask is used in IC fabrication Since the process is costly, mask ROM is used when the needed volume is high and it is absolutely certain that the contents will not change The main advantage of mask ROM is its cost, since it is significantly cheaper than other kinds of ROM, but if an error in the data/code is found, the entire batch must be thrown away 30

31 Appendix SRAM (Static RAM) Storage cells in static RAM memory are made of flip-flops and therefore do not require refreshing in order to keep their data The problem with the use of flip-flops for storage cells is that each cell require at least 6 transistors to build, and the cell holds only 1 bit of data In recent years, the cells have been made of 4 transistors, which still is too many The use of 4-transistor cells plus the use of CMOS technology has given birth to a high capacity SRAM, but its capacity is far below DRAM 31

32 Appendix NV-RAM (Nonvolatile RAM) NV-RAM combines the best of RAM and ROM The read and write ability of RAM, plus the nonvolatility of ROM NV-RAM chip internally is made of the following components It uses extremely power-efficient SRAM cells built out of CMOS It uses an internal lithium battery as a backup energy source It uses an intelligent control circuitry o The main job of this control circuitry is to monitor the V cc pin constantly to detect loss of the external power supply 32

33 Appendix DRAM (Dynamic RAM) Dynamic RAM uses a capacitor to store each bit It cuts down the number of transistors needed to build the cell It requires constant refreshing due to leakage The advantages and disadvantages of DRAM memory The major advantages are high density (capacity), cheaper cost per bit, and lower power consumption per bit The disadvantages is that o it must be refreshed periodically, due to the fact that the capacitor cell loses its charge; o While it is being refreshed, the data cannot be accessed In DRAM there is a problem of packing a large number of cells into a single chip with the normal number of pins assigned to addresses Using conventional method of data access, large number of pins defeats the purpose of high density and small packaging o For example, a 64K-bit chip (64K 1) must have 16 address lines and 1 data line, requiring 16 pins to send in the address The method used is to split the address in half and send in each half of the address through the same pins, thereby requiringcfewer address pins 33

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