ENGG3380: Computer Organization and Design Lab5: Microprogrammed Control

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1 ENGG330: Computer Organization and Design Lab5: Microprogrammed Control School of Engineering, University of Guelph Winter Objectives: The objectives of this lab are to: Start Date: Week #5 201 Due Date: Week #6 201 Acquaint you with two common methods for CPU control circuit design. Design a microprogrammed control circuit. Implement a mock-up of this circuit using the FPGA board. 2 CPU Control Design The datapath of a CPU is the circuit that contains, transfers and performs operations of program data. It should have at least a register file, an ALU, a method to communicate between the two (internal bus), and a method to allow the CPU to communicate with the outside world to get new data or send back the data after it s been processed (external bus). The datapath has much logic for computation of numbers required in the flow of software, but not the means to control the flow itself. The control unit of a CPU is what makes the datapath tick. It generates all control signals and plugs into the datapath to produce the desired behavior. While there are a plethora of control implementations out there, they are divided into two major categories: Hardwired. Microprogrammed. Hardwired control was historically the first. Instruction sets were designed and hard-coded into CPU circuitry. Combinational logic was used directly to decode an instruction contained in the instruction register (IR) into the control signals required to execute it. The logic combined the bit values in IR and the state of a cycle counter (step generator) to implement multi-cycle instruction operation as shown in Figure 1. As instruction sets grew in size, and instructions became more complicated (ie. entire string operations in a single instruction), creating hardwired controls in combinational logic became more and more complicated. Probability of mistakes also increased with size of the circuit, and errors in hardwired controls discovered following production required throwing the chips away and replacing them with new ones. The increasing cost of design, and the risks involved, led to an introduction of a more flexible circuit - the microprogrammed controller, shown in Figure 2. Each assembly level instruction at the software level is now decomposed internally into the number of required clock cycles to execute it on the datapath, and each clock cycle of an instruction on the datapath is

2 Figure 1: Hardwired Control CPU controlled by a microinstruction. In other words, a software program is rewritten from a series of multi-cycle instructions into sets of single cycle microinstructions as shown in Figure 3. All microcode instructions are stored like subroutines in a special memory inside the CPU - the microprogram store. A microinstruction is simply a concatenated set of control bits. A upc register is used to address the current ucode instruction in the store, and the uir is used to read off this instruction and connect the control bits it contains to the datapath. As software instructions may need different numbers of clock cycles to execute, there must also be some sort of ucode flow control implemented into the design - branches and jumps are also needed within microinstructions contained in the store. This functionality can easily be achieved by providing some of the bits within the microinstructions as signals for upc control. For example, at the end of each microprogram, representative of completion of one software instruction, upc should jump to ucode that facilitates the fetching of the next software instruction into the IR. In the simplest case, the OP code for an instruction can stand for the most significant bits of the upc jump address, and the flow control bits incorporated into each microinstruction can include signals for increment or reset of the upc register, or have the next address bits concatenated directly in the ucode, thus in some way contributing to a simple next address generator circuit. It is normal for ucode instructions to be very wide, depending on the control requirements of the datapath, especially when the datapath is pipelined very deep. In this case hundreds of control bits may be necessary. The benefit of defining all control functions using a memory block is to have the ability to easily reprogram it, to either add functionality or correct for mistakes.

3 Figure 2: Microprogrammed Control CPU 3 Microprogrammed Control In this lab, we will design and implement a microprogrammed control circuit. Since we will not have a datapath to plug this circuit into, we will emulate its operation on the FPGA board using our customary 7seg display to see the datapath control bit values presented at each clock cycle, and the switches to enter new software instructions to execute. Figure 4 is a top level diagram of the desired design. For the external signals, the switches are connected to IR. However, IR latches only on an enable signal, which is provided as one of the control signals by the microinstructions executed. The decoder translates the op code presented by IR to an address into the microcode store. For example, if the opcode field in IR is 4 bits wide, and at least 16 microcode instruction slots are reserved for each opcode, which gives an bit address space, the decoder can simply take the 4 opcode bits as an input and output an bit decoded address with the opcode in the 4 most significant bits, and 0 s in the rest of the lower positions. There must be some deterministic way to start the system, so a reset button (any IO board button) will be connected to reset upc at the users request. This effectively starts executing the first microinstruction in the store. This instruction should perform a fetch (present an enable for IR to latch on next clock, with datapath controls idle). As the microcode instructions are executed, control of upc is needed. You will either need to latch a new instruction value from IR to the upc - ie. perform a jump in the microcode to execute the instructions associated with the opcode in IR. Alternatively, upc should be incremented inside a microprogram for a particular opcode. The completion of an opcode microprogram should follow with resetting the upc to execute the fetch again. The clocking of the microprogrammed control unit will be carried using the manual clock button on the main FPGA board. The 50MHz clock will need to be connected only to the 7seg decoder

4 Figure 3: Assembly micro-instruction to facilitate appropriate digit scan timing. 4 Microprogrammed Control Unit Design and Implementation Connect the appropriate IO pins at your top level design entity to the 7seg digits, switches, 50MHz clock, manual clock, and a reset button. You may use the LEDs as well if you wish, eg. for debugging. The IR is bits wide, the opcode is on the four most significant bits. Enough address locations should be allocated inside the ucode store to support 15 opcodes plus the fetch, and contain all microcode per instruction as below. 16 bits of datapath control are required to be produced by the microinstructions, hence all 4 digits of the 7seg will be used to display them. In addition, you need to have the internal control signals (IR enable and MUX select) into your microinstructions alongside the datapath control. The bit order of those control signals is not important within a microinstruction, as long as they are appropriately connected within the controller and out to the datapath (ie. 7seg display). The sequence of datapath control signals that should appear on the 7seg is listed here with the relevant opcode. The all zero opcode is omitted here so as to allow you to place the fetch code at that address in the store, and make the decoder simple. You will test your controller on the FPGA board by selecting one of the above opcodes on the switches, then manually clocking the circuit to attain an appropriate output until end of sequence, and finally repeat the process as necessary for all opcodes. Do not forget to simulate your circuit thoroughly. If you already have valid simulations for underlying modules, such as the 7seg, a good practice is to copy the benchmarks together with the VHDL into your new design, so that all necessary simulations are available with your design.

5 CLOCK (Button) RESET SWITCHES Instruction Register En 1 bit " " MUX Sel 4 2 bits Logic Mapping "Decoder" upc Microcode Store Control Signals Microprogrammed Control Unit 7 Segment Driver Figure 4: Microprogrammed Control with Sequence Generator OpCode (Hex) ucode Sequence to datapath X1111 X2002 X2003 X1 X2004 X2 X2001 X1234 XF XABCD 5 Report When completed, you will hand in the following deliverables: 1. Title Page 2. A Block diagram of each design. 3. Simulation of each design. 4. VHDL code for each circuit designed (with comments). 5. VHDL code for simulation test-bench (with comments). 6. Report the resources used (LUTS, Flip Flops, e.t.c) for each implementation. 7. Justify your steps.

ENGG3380: Computer Organization and Design Lab4: Buses and Peripheral Devices

ENGG3380: Computer Organization and Design Lab4: Buses and Peripheral Devices School of Engineering, University of Guelph Winter 2017 1 Objectives: The purpose of this lab is : Learn basic bus design techniques.