Intel I/O Processor Software Conversion to Intel I/O Processor

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1 Intel I/O Processor Software Conversion to Intel I/O Processor Application Note August 2004 Order Number: US

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel s website at AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, icomp, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2004, Intel Corporation. All rights reserved. 2 Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

3 Contents Contents 1.0 Introduction Intel I/O Processor Architecture Overview Intel I/O Processor Memory Controller Architecture MCU Software Changes to Intel I/O Processor BIU Software Changes to Intel I/O Processor Intel I/O Processor Interrupt Controller Architecture ICU Software Changes to Intel I/O Processor Intel I/O Processor Private Device Control Architecture Private Device Control Software Changes to Intel I/O Processor PCI Express* to PCI-X Bridge Architecture PCI Express* to PCI-X Bridge Software Changes to PXH Intel XScale Core Access of PCI Express* to PCI-X Bridge Configuration Registers Bridge Initialization Requirements Peripheral Bus Interface Address Translation Unit GPIO and Serial Interfaces GPIO I 2 C Interface SMBus Interface UART Units Other Integrated Peripherals Summary...19 Figures 1 Intel I/O Processor Block Diagram...7 Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 3

4 Contents Tables 1 MCU Register Changes from Intel I/O Processor BIU Register Changes from Intel I/O Processor ICU Register Changes from Intel I/O Processor Private Device Control Registers Bridge Access Registers Bridge Initialization Registers PBI Register Changes from Intel I/O Processor ATU Register Changes from Intel I/O Processor GPIO Register Changes from Intel I/O Processor UART Registers Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

5 Contents Revision History Date Revision Description August Initial public release Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 5

6 Contents THIS PAGE INTENTIONALLY LEFT BLANK 6 Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

7 1.0 Introduction The Intel I/O processor (80332) is the first PCI Express* I/O processor in the Intel XScale microarchitecture family of I/O processors. The integrates two PCI Express* to PCI-X bridges with Intel I/O processor (80321) peripherals that have improved performance for next-generation products. The improvements over the provided in the include improved memory-controller architecture, higher-speed memory and internal busses, and a higher-performance interrupt controller. This application note describes these changes and the impact of converting a software stack to the Intel I/O Processor Architecture Overview As shown in Figure 1, the integrates the I/O peripherals of the as a PCI device connected internally to the PCI-X A-segment. The Intel XScale core accesses I/O devices through the ATU to the A-segment PCI-X bus, host memory through the ATU, and the PCI Express* port through the PCI Express* to PCI bridge. The core processor has access to the PCI Express*-to- PCI bridge configuration register space through this same path, using Type-0 configuration cycles. A simple model for the can be a connected to the secondary PCI interface of a PXH. The MCU and some peripherals of the are enhanced in the 80332, and some functionality of PXH is not provided in the However, the programming model of the two components is equivalent to the single-chip solution. Figure 1. Intel I/O Processor Block Diagram Intel XScale Core Bus Interface Unit 32-/64-bit DDR Interface Memory Controller UART Units 2 I 2 C Units 16-bit PBI Application Accelerator Unit 2.1 GB/s Internal Bus (266 MHz) Interrupt/ GPIO Unit 2-channel DMA Controller Timers ATU Message Unit Arbiter SMBus IOAPIC PCIe to PCI-X* Bridge A PCI-X IOP-Bus (133 MHz) PCIe x8 Performance Monitoring IOAPIC PCIe to PCI-X* Bridge B PCI-X Slot Bus (133 MHz) Arbiter/SHPC B Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 7

8 3.0 Intel I/O Processor Memory Controller Architecture The has significant improvements over the memory controller of the in both architecture and speed. The memory controller supports both DDR333 SDRAM for 2.7 GB/s bandwidth and DDR-II 400 MHz SDRAM for 3.2 GB/s bandwidth. Memory type is selected via a reset strap, MEM_TYPE. Note: DDR333 can be used only with the MHz and 667 MHz. DDR-II 400 can be used only with the MHz and 800 MHz. The architecture of the implements a dual-ported memory controller and Intel XScale core bus interface unit. This architecture allows core transactions targeting SDRAM to pass directly to the MCU, without crossing the internal bus. The memory controller also supports pipelined SDRAM transactions to reduce latency of back-to-back transactions. The MCU implements a programmable arbiter, allowing users to optimize the MCU behavior to best serve the application needs. Core processor transactions, targeting peripheral units or PCI devices, are directed across the internal bus by the Bus Interface Unit of the Intel XScale core. Peripheral units also have a separate port to the MCU for transactions, which are prioritized in the MCU against core processor transactions. 8 Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

9 3.1 MCU Software Changes to Intel I/O Processor The new MCU of the has additional registers for control of the arbiter and features. The control for both DDR and DDR-II impacts some register contents. Many registers remain unchanged; however, the internal bus addresses of the registers have been moved to accommodate additional registers. Note: The MCU is not backward-compatible to the Existing SDRAM initialization software needs modification to align register addresses to the MCU MMR map. The method for initializing the SDRAM through the Initialization and Control Registers must also be modified. The DDR SDRAM drive strength and I/O control registers are revised from the Two new MCU interrupt sources in the MCISR require interrupt service routines for the MCU to be updated. Registers that have control bits added or changed are listed in Table 1: Table 1. MCU Register Changes from Intel I/O Processor Register Description Change SDIR SDCR[1:0] S32SR MCISR MPTCR MPCR Various SDRAM Initialization SDRAM Control SDRAM 32-bit Region Size Interrupt Status Register MCU Port Transaction Count Register MCU Preemption Control I/O Drive Strength and Delay Control Registers Modified bit definition Default: N/A Added new fields and split into two registers Default: N/A New register for new feature Default: disabled New bits Default: no error New register for dual-ported MCU Default: IB=1, Core=12 New register for dual-ported MCU Default: disabled New MMR addresses and new definition Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 9

10 3.2 BIU Software Changes to Intel I/O Processor The new BIU of the has changed from the to implement the dual-port architecture to the new MCU. The registers of the BIU remain unchanged with the exception of addresses. The BIU registers of the are accessible only as memory-mapped registers and not as coprocessor registers, as was the case in the An additional register also exists for control of the BIU in the Note: The BIU is not backward-compatible to the Existing software must be modified to align register addresses to the BIU MMR map, instead of co-processor addressable registers. In addition, Table 2 lists the registers of the BIU that have been changed or added: Table 2. BIU Register Changes from Intel I/O Processor Register Description Change BIUSR BIU Status New bits added BIUCR BIU Control New register for dual-ported MCU 10Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

11 4.0 Intel I/O Processor Interrupt Controller Architecture The Interrupt Controller Unit (ICU) in the enhances what was implemented in the The ICU includes a vector port for both FIQ and IRQ interrupts, allowing the interrupt service routine to directly read the interrupt service routine vector, saving software overhead. The vector is calculated by the ICU, based on programmed values for Interrupt Service Routine Base Address, Interrupt Service Routine Size, and interrupt priorities. The ICU supports 64 interrupt sources (not all 64 sources are used) as compared to 32 in the ICU Software Changes to Intel I/O Processor The advanced vector generation features of the ICU are accessible by additional registers. An additional 32 interrupt sources are supported in the 80332, and a second set of registers for Control, Status, and Steering exist in the with the sources divided across these registers. The ICU registers exist as both MMR-mapped and co-processor 6 registers, as in the However, the ICU registers are remapped to different addresses. Note: The ICU is not backward-compatible to Existing software can be modified to take advantage of the interrupt vector generation feature utilizing the registers of the ICU which have been added (listed in Table 3): Table 3. ICU Register Changes from Intel I/O Processor Register Description Change INTCTL[1:0] Interrupt Mask Two registers for additional sources INTSTR[1:0] Interrupt Steering Two registers for additional sources IINTSRC[1:0] IRQ Pending Interrupt Sources Two registers for additional sources FINTSRC[1:0] FIQ Pending Interrupt Sources Two registers for additional sources IPR[3:0] Interrupt Priority New registers for interrupt priorities INTBASE Interrupt Service Routine Base Address New registers for vector generation INTSIZE Interrupt Service Routine Size New registers for vector generation IINTVEC IRQ Interrupt Vector New registers for vector generation FINTVEC FIQ Interrupt Vector New registers for vector generation PIRSR PCI Interrupt Routing Select Register New bits for additional interrupt steering flexibility Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 11

12 5.0 Intel I/O Processor Private Device Control Architecture Control of the private device mechanism of the is performed via registers residing in the PCI Express*-to-PCI bridge configuration mapped register space. 5.1 Private Device Control Software Changes to Intel I/O Processor The BINIT register within the bridge configuration space provides a single-bit control for enabling/disabling a group of device numbers as private devices. This bit allows inhibiting configuration access from the PCI Express* interface to PCI device numbers 0 through 9 (IDSEL tied to AD16 through AD25). No external RAIDIOS logic is required. Note: The private device control mechanism is not backward-compatible to RAIDIOS used with the In addition to enabling private devices, the BINIT register allows firmware to enable a private memory address space. This address space can be used in conjunction with the ATU s BAR3, to enable I/O controller access to the entire local memory, for data transfers to/from RAID cache. Interrupts from PCI devices are individually steered to the Interrupt Control Unit and core processor or the IOAPICs and host processor through the PCI Interrupt Routing Select Register (PIRSR). This register is enhanced over the register in the to accommodate additional PCI interrupt sources and routing control to the two IOAPICs. Table 4 lists the registers of the ATU that have been added: Table 4. Private Device Control Registers Register Description Unit Change PIRSR Interrupt Steering ATU BINIT Bridge Initialization Register Bridge Moved from ICU/GPIO in the 80321, and new bits added. New register/unit, for Private Device and Private Memory control 12Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

13 6.0 PCI Express* to PCI-X Bridge Architecture The integrates two PCI Express* to PCI-X bridges. These bridges are a direct integration of the PXH logic. However, some of the external pins are not supported in the The I/O processor portion of the is logically mapped to the secondary bus of one of the bridges, as a device on the secondary bus. The ATU IDSEL input is mapped to A-segment AD30, thereby defining the ATU as device 0xE on the A-segment. PCI address line AD30 is therefore not available for connecting PCI device IDSEL input on the A-Segment. 6.1 PCI Express* to PCI-X Bridge Software Changes to PXH The is actually identical to PXH from the programming interface, including PCI enumeration and configuration space. Every register has the same address and definition as in PXH. The PCI pad control registers are not in PXH for 80332, but reside in MMR space behind the ATU. Note: The PCI Express* to PCI-X bridges are software-compatible to those in PXH. 6.2 Intel XScale Core Access of PCI Express* to PCI-X Bridge Configuration Registers The core can access the bridge configuration space by generating Type-0 configuration cycles through the ATU to the A-segment PCI bus. By default, the bridge is configured to claim Type-0 configuration cycles, which do not fall within the Secondary-to-Subordinate bus number range. This capability is controlled in the BINIT register. At power-up, the bridge s Primary PCI bus number defaults to zero, and therefore a Type-0 configuration cycle to device number 0 (AD16) and function number 0, address the A-Segment Bridge configuration space. The B-Segment bridge is addressed as function number 2. The Primary and Secondary Bus Number registers of the bridge are mirrored within the ATU registers for firmware access. Firmware can read the Primary Bus Number register after host PCI enumeration has configured the bridge and use the value when generating Type-1 configuration cycles to access the bridge configuration registers. The Bridge Access Registers are described in Table 5. Table 5. Bridge Access Registers Register Description Change BINIT Bridge Initialization Register New register for PCI Configuration Access PEBPBNR Primary Bridge Bus Number Register New register PEBSABNR A-Bridge Secondary Bus Number Register New register PEBSBBNR B-Bridge Secondary Bus Number Register New register Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 13

14 6.3 Bridge Initialization Requirements As with the 80321, the Configuration Retry strap and function are implemented in the to allow firmware to initialize the processor before host PCI enumeration configures the processor. In the 80332, Configuration Retry is replicated in the ATU and Primary side (PCI Express* side) of the bridges. The firmware must clear both the ATU Configuration Retry bit and the Bridge Configuration Retry bit to enable host enumeration of the I/O processor and secondary PCI bus devices. The Configuration Retry bit in the bridges must be cleared in both the A and B segments. To clear the bit in the B segment, a Type-1 configuration cycle must be issued to the B segment bridge. Type-0 configuration cycles are used to access the A segment bridge configuration space. Table 6. Bridge Initialization Registers Register Description Change BINIT Bridge Initialization Register New register, for PCI Express* Configuration Retry Response control 14Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

15 7.0 Peripheral Bus Interface The Peripheral Bus Interface (PBI) of the is only 16-bits wide and includes only two address windows. Note: The PBI programming interface is backward-compatible to the for the registers and features except windows 2 5. The programming difference between the and the for the PBI interface is limited to the registers listed in Table 7. Table 7. PBI Register Changes from Intel I/O Processor Register Description Change PBBAR[5:2] Peripheral Bus Base Address Registers Not implemented in the PBLR[5:2] Peripheral Bus Limit Registers Not implemented in the PBDSCR PBI I/O Drive Strength New MMR address Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 15

16 8.0 Address Translation Unit The ATU has several differences compared to the ATU. These include an additional capability (VPD), removal of the PCI bus pad control, modification to the PIRSR, and new bus number registers for the bridge. A PCI Vital Product Data (VPD) extended capability has been added to the Address Translation Unit of the The capability of the registers is added to the ATU MMR map. The PCI Interrupt Routing Select register has been remapped in the with additional bits to handle more interrupts and steering options. The PCI Bus Drive Strength Control register is removed from the ATU, and the bus pad control is redefined in a dedicated register group. Bus number registers to mirror the bridge primary and secondary bus numbers have been added. ATU Configuration Write Interrupt is a new interrupt source, and there are three new bits in the ATUIMR and ATUISR to support this interrupt. Table 8 lists the registers that have changed in the from the Table 8. ATU Register Changes from Intel I/O Processor Register Description Change VPD_Cap_ID VPD Capability ID New register in ATU for optional capability VPD_Next_Item_Ptr VPD Next Capability Pointer New register in ATU for optional capability VPDAR VPD Address Register New register in ATU for optional capability VPDDR VPD Data Register New register in ATU for optional capability PIRSR PCI Interrupt Routing Select Register New MMR address, and additional bits various PCI Bus Drive Strength Control Registers New MMR address and definition PEBPBNR Primary Bridge Bus Number Register New register PEBSABNR A-Bridge Secondary Bus Number Register New register PEBSBBNR B-Bridge Secondary Bus Number Register New register PCSR[4] Reset Peripheral Bus control bit Not implemented in the ATU ATUCMD[10] Interrupt Disable bit New bit to support PCI v2.3 ATUSR[3] Interrupt Status bit New bit to support PCI v2.3 ATUISR[17:15] ATUIMR[14:12] ATU Interrupt Status Register ATU Interrupt Mask Register New status bits to support ATU Configuration Register Write Interrupt New mask bits to support ATU Configuration Register Write Interrupt 16Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

17 9.0 GPIO and Serial Interfaces The includes eight GPIOs, two backward-compatible I 2 C interfaces, one SMBus interface, and two UARTs. 9.1 GPIO The includes eight GPIOs. These GPIOs are multiplexed with the serial interfaces as in the The GPIO registers are remapped out of the Interrupt Control Unit MMR section, and bits have been added to control the new GPIO pins. An additional register has been added to control the multiplexing with the SMBus interface. Table 9 lists the register changes. Table 9. GPIO Register Changes from Intel I/O Processor Register Description Change GPOE GPIO Output Enable Register New MMR address GPID GPIO Input Data Register New MMR address GPOD GPIO Output Data Register New MMR address SMBER SMBus Enable Register New register for SMBus multiplexing control. Enabled by default. 9.2 I 2 C Interface The integrates two I 2 C interfaces that are backward-compatible to the These are unchanged in function and register address. 9.3 SMBus Interface The integrates one SMBus slave interface. This interface provides access to the PCI Express*-to-PCI bridge configuration registers as well as the IOAPICs and SHPC. This interface does not support access to the I/O peripherals, such as the ATU, MCU, and DMA. The SMBus is multiplexed with one of the I 2 C interfaces, limiting operation to one I 2 C interface when the SMBus interface is enabled. SMBus is enabled by default see Table 9. The SMBus interface uses the same implementation as PXH. Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 17

18 9.4 UART Units These units are mapped to MMR space, and are 4-pin UARTs (RXD, TXD, CTS# and RTS#), that are multiplexed with four GPIOs each. The registers for the UARTs are listed in Table 10. Note: Two UARTs are integrated in the that did not exist in the Table 10. UART Registers Register 1 Description Change UxRBR UART Receive Buffer New register UxTHR UART Transmit Buffer New register UxIER UART Interrupt Enable New register UxIIR/UxFCR UART Interrupt Status (Rd)/UART FIFO Control (Wr) New register UxLCR UART Line Control New register UxMCR UART Modem Control New register UxLSR UART Line Status New register UxMSR UART Modem Status New register UxSPR UART Scratch Pad New register UxDLL UART Divisor Latch Low New register UxDLH UART Divisor Latch High New register UxFOR UART FIFO Occupancy New register UxABR UART Autobaud Control New register UxACR UART Autobaud Count New register Note: 1. x indicates 0 or 1. Thus, UxRBR indicates both U0RBR and U1RBR. 18Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

19 10.0 Other Integrated Peripherals The includes a complete set of peripherals for RAID software, matching that of the These include timers, DMA, IARB, AAU, and MU. Note: These units remain unchanged in the 80332, except for the DMA, which does include the CRC32C generator which is not included in the Despite this exception, these peripherals are backwards-compatible Summary The integrates the PCI Express* to PCI-X bridges of the PXH with an I/O processor. No software differences exist between the and PXH; however, some functionality is limited due to reduced pin count. Some programming differences do exist between the and the 80321, as detailed in this application note. These include programming interface changes to the BIU, MCU, ICU, ATU, and PBI. Additional features in the exist in a backward-compatible mapping for newly integrated UART and bridges. Intel I/O Processor Software Conversion to Intel I/O Processor Application Note 19

20 THIS PAGE INTENTIONALLY LEFT BLANK 20Intel I/O Processor Software Conversion to Intel I/O Processor Application Note

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