ARM Processor. Dr. P. T. Karule. Professor. Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur

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Engineering, Nagpur 441 110 1 What is ARM? Advanced RISC Machine. 32-bit architecture.

1 ARM Processor Dr. P. T. Karule Professor Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur What is ARM? Advanced RISC Machine. 32-bit architecture. ARM is one of the most licensed processor cores in the world. Used especially in portable devices due to low power consumption and reasonable performance (MIPS / watt). 2 1

2 Why ARM here? High performance. Low code size. Low power consumption. More peripherals in single chip. Best suited for handheld battery operated devices Mobile application platform 3 Application of ARM 4 2

3 Bridge ARM block diagram 16 bit RAM 32 bit RAM Interrupt Controller nirq nfiq Peripherals I/O 8 bit ROM ARM Core 5 ARM Buses (architecture) Arbiter ARM Reset External ROM External RAM TIC External Bus Interface Decoder Bus Interface On-chip RAM/FLASH Timer Interrupt Controller Remap/ Pause AHB or ASB APB System Bus Peripheral Bus VPB(VLSI Peripherals Bus) AMBA(Advanced Micro controller Bus Architecture) AHB(Advanced High-performance Bus) APB(Advanced Peripheral Bus) ASB(Advanced System Bus) 6 3

4 ARM system architecture 7 ARM Processor cores: ARM6, ARM7, ARM9, ARM10, ARM11 Extensions: Thumb, El Segundo, Jazelle etc. IP-blocks: UART, GPIO, memory controllers, etc 8 4

5 ARM processor families 1 Halfword and signed halfword / byte support 4 Improved ARM/Thumb Interworking CLZ 5TE Jazelle Java bytecode execution 5TE J 2 3 System mode SA-110 SA-1110 Saturated maths DSP multiplyaccumulate instructions ARM9EJ-S ARM7EJ-S ARM926EJ-S ARM1026EJ-S Early ARM architectures Thumb instruction set ARM7TDMI ARM720T 5 ARM9TDMI ARM940T ARM1020E XScale ARM9E-S ARM966E-S SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support 6 ARM1136EJ-S 9 ARM Architecture 32-bit RISC-processor core (32-bit instructions) 37 pieces of 32-bit integer registers (16 available) Pipelined (ARM7: 3 stages) Cached (depending on the implementation) Von Neuman-type bus structure (ARM7), Harvard (ARM9) 8 / 16 / 32 -bit data types 7 modes of operation (usr, fiq, irq, svc, abt, sys, und) Simple structure -> reasonably good speed / power consumption ratio 10 5

6 ARM Internals Core Block Diagram 11 ARM Internals ARM core modes of operation: User (usr): Normal program execution state FIQ (fiq): Data transfer state (fast irq, DMA-type transfer) IRQ (iqr): Used for general interrupt services Supervisor (svc): Protected mode for operating system support Abort mode (abt): Selected when data or instruction fetch is aborted System (sys): Operating system privilege -mode for user Undefined (und): Selected when undefined instruction is fetched 12 6

7 ARM register set Register structure depends on mode of operation 16 pieces of 32-bit integer registers R0 - R15 are available in ARMmode (usr, user) R0 - R12 are general purpose registers R13 is Stack Pointer (SP) R14 is subroutine Link Register Holds the value of R15 when BLinstruction is executed R15 is Program Counter (PC) R16 is state register (CPSR,Current Program Status Register) 13 Data Types Byte, halfword, and word (aligned) signed and un-signed integers all data operations are performed on word quantities load and store operations transfer bytes, halfwords, and words to and from memory (zero- or sign-extending) ARM instructions are exact one word and aligned on a 4-byte boundary (Thumb instructions are exact one halfword) Memory and address a flat space of 2 32 bytes little-endian (1 st btye is the least significant byte) or big-endian (1 st byte is the most significant byte) ARM can support either one or both (need a hardware input to configure the endianness) 14 7

8 BIGEND The BIGEND input sets whether the ARM7 treats words in memory as being stored in Big Endian or Little Endian format Little Endian (LSB at lower address) bit 31 bit 0 Byte 3 Byte 2 Byte 1 Byte 0 Big Endian (MSB at lower address) bit 31 bit 0 Byte 0 Byte 1 Byte 2 Byte 3 15 BIGEND Little Endian E.g. 32 bit data= h Big Endian E.g. 32 bit data= h H H H H H H H H 16 8

Processor Modes Mode changes may be made under software control or may be caused by external interrupts or exception processing. Most application programs will execute in User mode.

9 Processor Modes Mode changes may be made under software control or may be caused by external interrupts or exception processing. Most application programs will execute in User mode. Other privileged modes will be entered to service interrupts or exceptions or to access protected resources: 17 Register Organization registers are arranged into several banks, being governed by the processor mode. Each mode can access a particular set of r0-r12 registers a particular r13 (the stack pointer) and r14 (link register) r15 (the program counter) cpsr (the current program status register) privileged modes can also access a particular spsr (saved program status register) 18 9

10 Register Example: User to FIQ Mode User Mode FIQ Mode Registers in use Registers in use r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq spsr_fiq EXCEPTION Return address calculated from User mode PC value and stored in FIQ mode LR User mode CPSR copied to FIQ mode SPSR r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc) cpsr spsr_fiq 19 Accessing Registers using ARM Instructions No breakdown of currently accessible registers. All instructions can access r0-r14 directly. Most instructions also allow use of the PC. Read from PC: the address of the inst. + 8 (or 12) Write to PC: bit[1:0] must be 00 Specific instructions to allow access to CPSR and SPSR. Note : When in a privileged mode, it is also possible to load / store the (banked out) user mode registers to or from memory

Agenda. ARM Core Data Flow Model Registers Program Status Register Pipeline Exceptions Core Extensions ARM Architecture Revision

Agenda. ARM Core Data Flow Model Registers Program Status Register Pipeline Exceptions Core Extensions ARM Architecture Revision Agenda ARM Processor ARM Core Data Flow Model Registers Program Status Register Pipeline Exceptions Core Extensions ARM Architecture Revision www.clabsys.com ARM Core Data Flow Model Registers ARM has