Cell Broadband Engine. Spencer Dennis Nicholas Barlow

Transcription

1 Cell Broadband Engine Spencer Dennis Nicholas Barlow

2 The Cell Processor Objective: [to bring] supercomputer power to everyday life Bridge the gap between conventional CPU s and high performance GPU s

3 History Original patent application in 2002 Generations 90 nm nm (PowerXCell 8i) 45 nm

4 Cost $400 Million to develop Team of 400 engineers STI Design Center Sony Toshiba IBM Design

5 PS3 Employed as CPU Clocked at 3.2 GHz theoretical maximum performance of GFLOPS Utilized alongside NVIDIA RSX 'Reality Synthesizer' GPU Complimented graphical performance

6 8 Synergistic Processing Elements (SPE) Single Dual Issue Power Processing Element (PPE) Memory IO Controller (MIC) Element Interconnect Bus (EIB) Memory IO Controller (MIC) Bus Interface Controller (BIC) Architecture Overview

7 SPU/SPE Synergistic Processing Unit/Element SXU - Synergistic Execution Unit LS - Local Store SMF - Synergistic Memory Frontend EIB - Element Interconnect Bus PPE - Power Processing Element MIC - Memory IO Controller BIC - Bus Interface Controller

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10 Synergistic Processing Element (SPE) 128-bit dual-issue SIMD dataflow Single Instruction Multiple Data Optimized for data-level parallelism Designed for vectorized floating point calculations.

11 SPE Continued Workhorses of the Processor Handle most of the computational workload Each contains its own Instruction + Data Memory Local Store Embedded SRAM

12 Responsible for governing SPEs Extensions of the PPE Shares main memory with SPE can initiate accesses for SPE cores Power Architecture Implements Power Architecture Hypervisor can run multiple operating systems concurrently Memory (1st generation) 32KB split L1 instruction & Data cache unified 512KB L2 Cache Power Processor Element (PPE)

13 Element Interconnect Bus High bandwidth internal bus 1st generation: 96 Bytes/cycle 4 16B rings can handle up to 3 simultaneous data transfers 12 on and off ramps Each SPE + PPE memory controller 2 Off-chip I/O interfaces

14 Memory Flow Controller Asynchronous Memory Controller Retrieves data from main memory to SPE s local storage & PPE s Cache. Supports two Rambus XDR memory banks

15 Bus Interface Controller Provides asynchronous interface between EIB and IO interfaces Two flexible IO interfaces to rest of system One Interface can be reconfigured to provide Symmetric Multiprocessing (SMP) interface Contains pervasive unit provides test, debug and monitoring functionality Chip level error checking provides clock generation & distribution control Power on Reset Unit (POR) Responsible for unit initialization Performance monitoring Power Management Unit (PMU) Allows software controlled power reduction Thermal Management Unit (TMU)

16 Developing for Cell Octopiler Takes high level sequential code and parallelizes it to optimize it for a multiprocessor system High level languages Divides code nine ways 8 sets of instructions are written for the SPE s The final set is written for the Power PC PPE GCC IBM sourced plugins for cell PPU/SPU development

17 SPU ISA

18 SPU ISA (cont d)

19 Applications (In Depth) Console Gaming PS3 PPE controls 6 SPE s delegating tasks 1 SPE is OS reserved, 1SPE is redundant Supercomputing IBM BladeCenter QS Series Easy Scalability Password cracking High parallelism allows for high floating point brute force performance

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21 Conclusion Discontinued in 2009 Difficult development environment Programmer managed SPE memory Explicit parallelism Two separate ISAs Idea still lives on General Purpose GPU Intel Larabee Architecture Intel Many Integrated Core Architecture AMD FireStream Nvidia Tesla

22 01.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C F F2C44/$file/SPU_ISA_v1.2_27Jan2007_pub.pdf ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber= Articles/Archive/sabl/2006/Jul/CellProcessorPotential.pdf References