Cortex-A75 and Cortex-A55 DynamIQ processors Powering applications from mobile to autonomous driving

Transcription

1 Cortex-A75 and Cortex-A55 DynamIQ processors Powering applications from mobile to autonomous driving Stefan Rosinger Director, Product Management Arm Arm TechCon 2017

2 Agenda Market growth and trends DynamIQ technology Arm Cortex-A75 and Cortex-A55 processors 2

3 Arm: The industry s architecture of choice Extraordinary growth from sensors to server 50 billion 100 billion 50 billion chips shipped chips shipped chips expected to ship 4 years 4 years 22 years

4 Arm focused on key growth market segments Mobile Client Infrastructure Embedded & Automotive 4

5 Looking ahead from edge to cloud Cortex beyond mobile Mixed reality Safe and autonomous Hyper-efficient Secure private compute 5

6 Arm architecture for total computing Cortex-A Highest performance Cortex-R Faster responsiveness Cortex-M Smallest/lowest power SecurCore Tamper resistant Designed for high-level operating systems Designed for high performance, hard realtime applications Designed for discrete processing and microcontrollers Designed for physical security 6

7 Innovating for the scalable future Key Arm technologies Expanding Arm technology processor architecture for broad market Up to 8 CPUs Octacore smartphones Dual cluster Heterogeneous processing Nearly Unlimited design spectrum Covers all existing use cases DynamIQ cluster Dynamic flexibility

8 DynamIQ technology

9 Imagine the possibilities Video 9

10 Arm DynamIQ Rearchitecting the compute experience Designed from the ground up for AI Large system performance uplift More intelligent systems 10

11 Accelerating AI adoption everywhere DynamIQ boosting AI/ML performance with Arm Compute Library, new CPUs and GPU Mali GPU Cortex-A CPUs Dedicated processor instructions and optimized libraries for AI 11 Accelerator Improved access to acceleration

12 Uncompromised performance at all tiers DynamIQ increases big.little performance levels High end Mid Entry level 4b+4L Laptop-ready compute performance 1b+7L 2x single-thread performance (vs. today s octacore) 4L Elevating your user experience 12 Example configurations shown

13 Intelligent power savings C P U C P U CPU Finer-grained speed control Power States Faster on/sleep/off CPU memory Autonomous power management 13

14 DynamIQ: New single cluster design for new cores DynamIQ big.little systems Greater product differentiation and scalability Improved energy efficiency and performance SW compatibility with Energy Aware Scheduling (EAS) Private L2 and shared L3 caches SCU Cortex-A75 32b/64b Core Private L2 cache.. Peripheral port Cortex-A55 32b/64b Core Private L2 cache Async bridges Local cache close to processors L3 cache shared between all cores ACP AMBA4 ACE DynamIQ Shared Unit (DSU) Shared L3 cache DynamIQ Shared Unit (DSU) Contains L3, Snoop Control Unit (SCU) and all cluster interfaces 1b+7L 2b+6L 4b+4L 1b+2L 1b+3L 1b+4L 14 Example: DynamIQ big.little configurations

15 Cortex-A75 and Cortex-A55 CPUs

16 New DynamIQ-based CPUs for new possibilities Cortex-A75 processor >50% more performance compared to current devices Cortex-A55 processor 2.5x higher power efficiency compared to current devices Estimated device performance using SPECINT2006, final device results may vary Comparison using Cortex-A73 at 2.4GHz vs Cortex-A75 at 3GHz Comparison using Cortex-A53 in 28nm devices vs Cortex-A55 in 16nm devices 16

17 New DynamIQ-based CPUs for new possibilities Cortex-A75 Cortex-A55 Geekbench v4 1.34x Geekbench v4 1.22x Octane x Octane x LMBench memcpy 1.16x LMBench memcpy 1.97x SPECFP x SPECFP x SPECINT x SPECINT x Baseline to Cortex-A73 Baseline to Cortex-A53 All comparisons at iso process and frequency All comparisons at iso process and frequency 17

18 L1 memory system Common features 4-way set associative VIPT with PIPT programmer s view Improved prefetchers Cortex-A75 64KB Wider load-store than Cortex-A73 Support Read-after-Write OoO with filtering Cortex-A55 L1 TLB L1 Data Cache Store Buffer Prefetcher L2 TLB L2 Cache 16KB / 32KB / 64KB Improved store buffer bandwidth to L1 Larger 16-entry L1-TLB 18

19 L2 memory system Common features Private L2 cache in each core Running at core speed Exclusive data cache Cache stashing into the L2 Non-blocking 1024-entry TLB for hit-under-miss Cortex-A75 L1 TLB L1 Data Cache Store Buffer Prefetcher L2 TLB L2 Cache 256KB / 512KB Cortex-A55 0KB / 64KB / 128KB / 256KB 19

20 DynamIQ Shared Unit (DSU) Support for multiple performance domains Core 0 DynamIQ cluster 0-7 Cores Core 7 Latency and bandwidth optimizations DynamIQ Shared Unit (DSU) Streamlines traffic across bridges Snoop filter L3 Cache Asynchronous bridges Bus I/F ACP and peripheral port I/F Power Management Advanced power management features Supports large amounts of local memory Scalable interfaces for edge to cloud applications Low latency interfaces for closely coupled accelerators 20

21 System solutions

22 Premium mobile system Complete system IP portfolio from Arm GIC-600 I/O Coherent Masters Built for premium NIC-450 Mali G72 Mali- V61 Mali- Display Scaled to mid-range and entry level Cortex-A75 Cortex-A55 MMU-500 MMU-500 Incorporates the latest features Security with Arm TrustZone Sensor hub and acceleration DMC- 500 LPDDR4 DMC- 500 Memory system, integrated TrustZone CoreLink CCI-550 Sensor fusion hub Cortex-M7 Crypto Cell- 712 Interconnect NIC-450 Peripherals 22

23 The best upgrade path for mid-range devices Power, performance and area of octa-core CPU systems Area Integer (SPECINT2000) Floating Point (SPECFP2000) 2.34 Memory Streaming (JMCStream) x performance (compared to LITTLE only) Cortex-A53 Octa A53 A53 L2 A53 A53 A53 A53 L2 Coherent Interconnect A53 A53 Cortex-A55 Octa A55 A55 A55 A55 A55 A55 A55 A55 L3 Interconnect Cortex-A75/Cortex-A55 Octa A75 A55 A55 A55 A55 A55 A55 A55 L3 Interconnect Same or similar area (compared to Cortex-A53 LITTLE only) 23

24 Safer autonomous systems DynamIQ supports safety critical industrial and automotive systems Resilient systems Allowing systems to operate safely under failure Adaptive compute Uncompromised performance for autonomous systems Faster responsiveness Quicker safety critical decision-making 24

25 Diverse range of automotive compute solutions Powertrain Cortex-R52 Real time Homogeneous multi-core Vision ADAS Cortex-A55 + Cortex-R52 Heterogeneous multi-core Computer vision Control Autonomous driving Cortex-A75 + Cortex-R52 High performance multi-cluster Machine learning Functional safety Infotainment Cortex-A75 + Cortex-A55 Energy-aware scheduling Rich OS Security Central body control Low power Efficient performance Scalable Other modules V2X Chassis Security Radar Sensor Audio Cortex-M7, Cortex-M0+ 25

26 Safety and reliability with DynamIQ Compute performance for ADAS and IVI Higher performance for autonomous cars Faster responsiveness for safety critical tasks Functional safety Autonomous system Sense Perceive Decide Actuate SoC ASIL D systematic capability Advanced RAS architectural features Industry s broadest functional safety capable CPU IP portfolio Cortex-M Sensors Cortex-A CPU CPU L2 L2 Cache L2 L2 Cache Cache L3 Cache Application cores Cortex-R Lock-step core Safety Island 26

27 Power-constrained ADAS platform big GIC-600 ELA LITTLE ELA Cortex-A75 Cortex-A55 DSU DSU CoreLink CCI-550 Mali-G72 GPU Safety island DCLS Cortex-R52 CoreLink NIC-450 Security Enclave CryptoCell 312 SRAM DMA I/O Isolated for highest reliability & integrity System monitoring, diagnostics & recovery Failsafe communication Mali- V61 MMU-500 Assertive Display Mali-Display CoreLink NIC-450 Mali-C71 CoreLink NIC-450 Peripherals DMC LPDDR4x 27

28 Summary DynamIQ technology is enabling more capable SoCs for key growth markets Brings new device solutions for all markets & tiers from mobile to automotive, and beyond Cortex-A75: Breakthrough performance Cortex-A55: Efficiency redefined Elevating the user experience for the premium doubling the performance levels for the mid-range and mass-market New single cluster approach for better scalability and flexibility New DynamIQ Shared Unit, new memory hierarchy, new advanced power management features 28

29 Arm architecture for total computing SoC IP Ecosystem Security Intelligence Widest, most proven choice of IP to meet diverse PPA needs Worlds #1 embedded software ecosystem Support across all Cortex-A and some Cortex-M CPUs Arm Compute Library & DynamIQ accelerate intelligence at the edge 28 billion Arm-based embedded chips shipped* 29 *As of CY Q1 2017

30 For further information Find demos and more information at the Arm booth (402) and Mbed booth (712) At TechCon After TechCon Advanced IP solutions to enable the autonomous automotive revolution James Scobie Functional Safety: What is Arm doing to support this critical capability? Neil Stroud Cortex-A75 and Cortex-A55 DynamIQ processors powering applications from mobile to autonomous drive Stefan Rosinger Panel: What does functional safety mean for the automotive supply chain? Moderator Andrew Moore 30

31 Thank You! Danke! Merci! 谢谢! ありがとう! Gracias! Kiitos! 31

32 The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. 32