SoC Platforms and CPU Cores
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1 SoC Platforms and CPU Cores COE838: Systems on Chip Design Dr. Gul N. Khan Electrical and Computer Engineering Ryerson University Overview SoC Platforms -- Xilinx Zynq-7000 SoC platform. Altera Cyclone(Arria)-V SoC platforms, DE1-SoC. ARM Cortex A9 Specs and Applications. Cortex-A9 Micro-architecture. Neon Media Processing Engine. SoC Platforms, and Cortex A9 Data and some Material from Chapter 3 of the Text by M.J. Flynn
2 SoC Platforms SoC Platforms can be of two categories: SoC FPGA Commercial and Specific SoC platforms employed by Apple, Samsung, Siemens, etc. SoC FPGA Platforms: Zynq-7000 by Xilinx Cyclone-V and Arria-V platforms by Altera G. Khan SoC Platform and CPU Cores Page: 2
3 Xilinx SoC Development Platforms G. Khan SoC Platform and CPU Cores Page: 3
4 Zynq SoC G. Khan SoC Platform and CPU Cores Page: 4
5 ZYNQ Platforms 7000 AVB: Audio Video Bridging G. Khan SoC Platform and CPU Cores Page: 5
6 Zynq 7000 SoC Platform CPU Core Processor Extensions L1 Cache L2 Cache On-Chip Memory Memory Interfaces Peripherals Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Dual ARM Cortex -A9 MPCore with CoreSight NEON & Single / Double Precision Floating Point for each processor 32 KB Instruction, 32 KB Data per processor 512 KB 256 KB DDR3, DDR3L, DDR2, LPDDR2, 2x Quad-SPI, NAND, NOR 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO Logic Cells 28K 74K 85K 125K 275K 350K 444K Block RAM 240 KB 380 KB 560 KB 1,060 KB 2,000 KB 2,180 KB 3,020 KB (Mb) DSP Slices ,020 Transceiver up to 4 up to 16 up to 16 up tp 16 4 (6.25 Gb/s) Count (12.5 Gb/s) (12.5 Gb/s) (12.5 Gb/s) (10.3 Gb/s) G. Khan SoC Platform and CPU Cores Page: 6
7 Cortex A9 Processing Configuration G. Khan SoC Platform and CPU Cores Page: 7
8 Cortex A9 based Processing System Programmable SoCs through dual Cortex A9 Hardened peripherals includes Ethernet, I2C, USB, and CAN; XPS support design clock domain setup, interrupts, DMAs, etc. External connections for the hardened peripherals AXI Interfaces Systems, peripherals, trace and debug clocks Hardened Zynq-EPP peripheral interfaces Interrupts Peripheral connections to Multiplexed I/O G. Khan SoC Platform and CPU Cores Page: 8
9 Cortex-A9 based Processing System AXI Interfaces General-Purpose 32-bit AXI Master/Slave Ports High-Speed 32/64-bit AXI Slave Ports 64-bit AXI Accelerator Coherency Port General purpose DMA controllers Systems, peripherals, trace and debug clocks Interrupts Peripheral connections to Multiplexed I/O G. Khan SoC Platform and CPU Cores Page: 9
10 Cortex A9 based Processing System Hardened Zynq-EPP peripheral interfaces Quad SPI/SRAM/NOR/NAND Flash Gigabit Ethernet USB 2.0 Secure Digital UART I2C SPI CAN GPIO Interrupts Peripheral connections to Multiplexed I/O G. Khan SoC Platform and CPU Cores Page: 10
11 Zynq-7000 AP SoC Development Tools G. Khan SoC Platform and CPU Cores Page: 11
12 Altera SoC Family FPGA G. Khan SoC Platform and CPU Cores Page: 12
13 Cyclone-V SX SoC FPGA Cyclone-V FPGA family is based on 1.1-V, 28nm technology High performance designs and SoC prototyping G. Khan SoC Platform and CPU Cores Page: 13
14 Stratix-V GX Family Stratix-V FPGA family is based on 0.85-V, 28-nm. High performance designs, high logic and memory-density designs, as well as ASIC prototyping. G. Khan SoC Platform and CPU Cores Page: 14
15 Arria-V SX SoC FPGA Arria-V FPGA family is based on 1.1V, 28nm It can prototype/implement ARM Cortex A9 CPU based SoCs G. Khan SoC Platform and CPU Cores Page: 15
16 Avalon Bus Module The Avalon bus module (an Avalon bus) is a unit of active logic that takes the place of passive, metal bus lines on a physical PCB. G. Khan SoC Platform and CPU Cores Page: 16
17 Avalon Bus Avalon bus is on-chip bus architecture that accommodate the SOC environment. The interface to peripherals is synchronous with the Avalon clock. Multiplexers (not tri-state buffers) inside the bus determine which signals drive which peripheral. Peripherals are never required to tri-state their outputs. Address, data and control signals use separate, dedicated ports. It simplifies the design of peripherals as they don t need to decode address and data bus cycles as well as disable its outputs when it is not selected. G. Khan SoC Platform and CPU Cores Page: 17
18 Avalon Bus based System Module System Module integrated with user Logic into an Altera FPGA. G. Khan SoC Platform and CPU Cores Page: 18
19 Slave Arbitrator Avalon bus module contains one slave arbitrator for each shared slave port. Slave arbitrator performs the following. Defines control, address, and data paths from multiple master ports to the slave port and specifies the arbitration mechanism to use when multiple masters contend for a slave at the same time. At any given time, selects which master port has access to the slave port and forces all other contending masters (if any) to wait, based on the arbitration assignments. Controls the slave port - based on address, data & control signals presented by the currently selected master port. G. Khan SoC Platform and CPU Cores Page: 19
20 Altera Arria-V SoC Platform ARM -based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. G. Khan SoC Platform and CPU Cores Page: 20
21 Cyclone-V SoC Platform Cyclone-V SoCs reduce system power, cost, and board size while increasing system performance by integrating discrete processor, FPGA, and DSP functions into a single, user customizable ARM-based (SoC) G. Khan SoC Platform and CPU Cores Page: 21
22 Arria HPS: Hard Processor System 1.05 GHz, dual-core ARM Cortex-A9 MPCore processor including: 32 KB of L1 instruction cache, 32 KB of L1 data cache Single/double-precision FPU and NEON TM media engine 512 KB of shared L2 cache with error correction code (ECC) support 64 KB of scratch RAM with ECC support Multiport SDRAM controller with support for DDR2, DDR3, etc. QSPI and NAND flash controller with DMA SD/SDIO/MMC controller with DMA 2x 10/100/1000 Ethernet media access control (MAC) with DMA 2x USB On-The-Go (OTG) controller with DMA 4x I 2 C controller and 2x UART 2x (SPI) master peripherals, 2x SPI slave peripherals Up to 134 general-purpose I/O (GPIO) 7x general-purpose timers and 4 watchdog timers G. Khan SoC Platform and CPU Cores Page: 22
23 Cyclone HPS (Hard Processor System 925 MHz, dual-core ARM Cortex-A9 MPCore processor including: 32 KB of L1 instruction cache, 32 KB of L1 data cache Single/double-precision FPUand NEON TM media engine 512 KB of shared L2 cache with error correction code (ECC) support 64 KB of scratch RAM with ECC support Multiport SDRAM controller with support for DDR2, DDR3, etc. QSPI and NAND flash controller with DMA SD/SDIO/MMC controller with DMA 2x 10/100/1000 Ethernet media access control (MAC) with DMA 2x USB On-The-Go (OTG) controller with DMA 4x I 2 C controller and 2x UART 2x (SPI) master peripherals, 2x SPI slave peripherals Up to 134 general-purpose I/O (GPIO) 7x general-purpose timers and 4 watchdog timers G. Khan SoC Platform and CPU Cores Page: 23
24 HPS-to-FPGA Interconnect HPS and the FPGA can operate independently. Tightly coupled via AMBA bridges: IP bus masters in FPGA fabric have access to HPS bus slaves. HPS bus masters have access to bus slaves in FPGA fabric. Both bridges are AMBA AXI-3 compliant and support simultaneous read and write transactions. o Additional 32-bit light-weight HPS-to-FPGA bridge with low latency i/f between HPS and peripherals in FPGA fabric. o Six FPGA masters can share the HPS SDRAM controller with ARM Cortex A9 processor. o A9 processor can be used to configure FPGA fabric under program control via a dedicated 32-bit port. G. Khan SoC Platform and CPU Cores Page: 24
25 HPS-to-FPGA Interconnect HPS-to-FPGA: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth FPGA-to-HPS: configurable 32-, 64-, or 128-bit AMBA AXI interface optimized for high bandwidth Lightweight HPS-to-FPGA: 32-bit AMBA AXI interface optimized for low latency FPGA-to-HPS SDRAM controller: Configurable multiport interfaces with 6 command ports, 4x 64-bit read data ports and 4x 64-bit write data ports ~32-bit FPGA configuration manager G. Khan SoC Platform and CPU Cores Page: 25
26 DE1 SoC G. Khan SoC Platform and CPU Cores Page: 26
27 DE1-SoC Cyclone-V SoC 5CSEMA5F31 Device Dual-core ARM Cortex-A9 (HPS) 85K programmable logic elements 4,450Kbits embedded memory 6 fractional PLLs 2 hard memory controllers Quad serial configuration device EPCQ256 On-board USB-Blaster II 64MB (32Mx16) SDRAM on FPGA 1GB (2x256Mx16) DDR3 SDRAM on HPS Micro SD card socket on HPS G. Khan SoC Platform and CPU Cores Page: 27
28 DE1-SoC HPS HPS Hard Processor System 800MHz Dual-core ARM Cortex-A9 MPCore processor 1GB DDR3 SDRAM (32-bit data bus) 1 Gigabit Ethernet 2-port USB Host Micro SD card socket Accelerometer (I2C interface + interrupt) UART to USB Warm reset and cold reset A user LED G. Khan SoC Platform and CPU Cores Page: 28
29 SoC Model and Processors Idealized (conservative performance) processors selected by function and real-time requirements G. Khan SoC Platform and CPU Cores Page: 29
30 SoC Processor Selection The process of CPU selection is limited as there can be a real time requirement that must be met by one of the processors or an accelerator: This will become a primary consideration at an early stage in the initial SOC design phase. The processor selection and parameterization result in an initial SoC deign. Initial SoC design appears to fully satisfy all the functional and performance requirements set out in the specifications. Such design has some advantages. Cost reduction in terms of system - level integration Design reuse Creating an exact fit for a CPU/peripheral combination Providing future expansion protection against discontinuation G. Khan SoC Platform and CPU Cores Page: 30
31 Processor Core Selection G. Khan SoC Platform and CPU Cores Page: 31
32 Soft Processors OpenRISC. A free and open - source soft - core processor. Leon4. Another free and open - source soft - core processor that implements a complete SPARC v8 (ISA) OpenSPARC. SPARC T1 core supports 1-4 threads on FPGAs Nios II(fast) MicroBlaze OpenRISC Leon4 Open source No No Yes Yes Hardware FPU Yes Yes No Yes Bus standard Avalon CoreConnect WISHBONE AMBA Integer div. unit Yes Yes No Yes Custom Yes Yes Yes Yes coprocessor/insts. Maximum freq on FPGA (MHz) Max-MIPS on/fpga Resources 1800 LE 1650 slices 2900 slices 4000 slices Area estimate 1500 A 800 A 1400 A 1900 A G. Khan SoC Platform and CPU Cores Page: 32
33 Soft Processors OpenRISC: A free and open - source soft - core processor. Leon4: Another free and open - source soft - core processor that implements a complete SPARC v8 OpenSPARC: SPARC T1 core supports 1-4 threads on FPGAs These Processors are based on a 32-bit Reduced Instruction Set Computer (RISC) architecture Single-issue 5-stage pipelines and have configurable datainstruction caches Support for the gnu (GCC) compiler tool chain. They also feature bus architectures suitable for adding extra processing units as slaves or masters. Some even go further and allow the addition of custom instructions and/or coprocessors. G. Khan SoC Platform and CPU Cores Page: 33
34 More Soft Processors G. Khan SoC Platform and CPU Cores Page: 34
35 SoC Processor: ARM Cortex A9 Implementation size, performance, and very low power consumption are the key attributes of ARM architecture. ARM CPUs are RISC type Load/store architecture Simple addressing The ARM Cortex-A9 processor is the high performance choice from a family of low power, cost-sensitive CPU devices. The Cortex-A9 micro-architecture is delivered either as a Cortex-A9 single core processor or a scalable multi-core processor i.e. Cortex-A9 MPCore processor. G. Khan SoC Platform and CPU Cores Page: 35
36 Not to scale ARM Public Processor Roadmap ARM 7, 9, 11 Application Real-time Microcontroller ARM11 (MPCore) ARM926EJ-S ARM9 EmbeddedICE CoreSight ~600 to 1 GHz 200+ MHz Cortex-R4F Cortex-R4 Up to 2.5 GHz Up to 2 GHz Cortex-A8 Cortex-A9 (MPCore) Cortex-A5 Cortex-A57 Cortex-A53 Cortex-A15 Cortex-A9 (Dual) Cortex-A7 Cortex-R7 Cortex-R5 V8 (64 Bit ARM7 ARM7TDMI 200+ MHz Cortex-M MHz Cortex -M3 SC300 Cortex-M1 Cortex-M0Cortex-M0+ 50 MHz Cortex-M0 DesignStart
37 Cortex-A9 Usage A 32-bit system-on-chip designed by Apple and manufactured by Samsung. A5 consists of a dual-core ARM Cortex-A9 CPU with NEON SIMD accelerator and a dual core GPU. G. Khan SoC Platform and CPU Cores Page: 37
38 Cortex-A9 Usage Up to 2GHz Quad-core ARM Cortex-A9 MPCore G. Khan SoC Platform and CPU Cores Page: 38
39 Dual Core A9 CPU for the SoC DE1-SoC MPU subsystem includes: Two Cortex-A9 processors L2 cache and memory subsystem SCU: Snoop Control Unit Accelerator Coherency Port (ACP) Debug functions G. Khan SoC Platform and CPU Cores Page: 39
40 G. Khan SoC Platform and CPU Cores Page: 40
41 Cortex-A9 Micro-architecture Rename Issue Execute Writeback Decode Instruction Fetch Memory G. Khan SoC Platform and CPU Cores Page: 41
42 x G. Khan SoC Platform and CPU Cores Page: 42
43 - G. Khan SoC Platform and CPU Cores Page: 43
44 G. Khan SoC Platform and CPU Cores Page: 44
45 Issue can be fed a maximum of 2 instructions/cycle Issue can dispatch up to 4 instructions per cycle Out of order selection of instructions from the queue G. Khan SoC Platform and CPU Cores Page: 45
46 G. Khan SoC Platform and CPU Cores Page: 46
47 NEON technology supports instructions targeted primarily at audio, video, 3D graphics, image and speech processing. G. Khan SoC Platform and CPU Cores Page: 47
48 The Cortex-A9 NEON MPE (Media Processing Engine) features: SIMD and scalar single-precision floating-point computation Scalar double-precision floating-point computation SIMD and scalar half-precision floating-point conversion 8, 16, 32, and 64-bit signed and unsigned integer SIMD computation 8 or 16-bit polynomial computation for single-bit coefficients Large, shared register file, addressable as: * thirty-two 32-bit S (single) registers * thirty-two 64-bit D (double) registers * sixteen 128-bit Q (quad) registers. G. Khan SoC Platform and CPU Cores Page: 48
49 G. Khan SoC Platform and CPU Cores Page: 49
50 -1/2 G. Khan SoC Platform and CPU Cores Page: 50
51 G. Khan SoC Platform and CPU Cores Page: 51
52 G. Khan SoC Platform and CPU Cores Page: 52
53 Instruction Cache Data Cache Instruction Cache Data Cache Instruction Cache Data Cache Instruction Cache Data Cache Accelerator Coherency Port L2 Cache Main Memory G. Khan SoC Platform and CPU Cores Page: 53
54 CPU D$ I$ AXI RW 64-bit bus Cortex A9 MPcore CPU D$ I$ SCU AXI RW 64-bit bus L2 Cache Main Memory ACP Virtually Indexed, Physically Tagged Physically Indexed, Physically Tagged G. Khan SoC Platform and CPU Cores Page: 54
55 Cortex A9 MPcore CPU CPU D$ I$ D$ I$ SCU ACP AXI RW 64-bit bus L2 Cache AXI RW 64-bit bus Main Memory G. Khan SoC Platform and CPU Cores Page: 55
56 SCU connects 1-4 Cortex-A9 processor cores to memory system through AXI interfaces. D$ I$ AXI RW 64-bit bus D$ I$ AXI RW 64-bit bus The SCU is an integral part of the cache memory systems and its functions are: Maintain data cache coherency between the Cortex-A9 processors Initiate L2 AXI memory accesses Arbitrate between Cortex-A9 processor cores requesting L2 accesses Manage ACP accesses. L2 Cache Main Memory The Cortex-A9 SCU does not support hardware management of coherency of the instruction cache. G. Khan SoC Platform and CPU Cores Page: 56
57 G. Khan SoC Platform and CPU Cores Page: 57
58 G. Khan SoC Platform and CPU Cores Page: 58
59 ACP allows level-3 interconnect masters e.g. ethernet media access controller, DMA and FPGA-to-HPS bridge to share data coherently with CPU. Read accesses to coherent memory regions always return the most current data, whether in L1, L2 cache, or the main memory. Similarly, write operations to coherent memory regions cause the SCU to forward coherent data to memory system. The ACP ID mapper is located between the L3 interconnect and the ACP. The ARM ACP port is designed to support up to 8 unique transactions concurrently, where FPGA fabric may have any number of masters requesting coherent transactions. G. Khan SoC Platform and CPU Cores Page: 59
60 Coherent Memory, SCU and ACP SCU maintains bidirectional coherency among the L1 data caches ensuring both CPUs access the most recent data. When a CPU writes to coherent memory location, SCU ensures that the data is coherent. SCU also monitors read operations from a coherent memory location. If the required data is already stored in the L1 caches, the data is returned directly to the requesting CPU. If the data is not in the L1 cache, the L2 cache checks its contents before the data is finally retrieved from the main memory. G. Khan SoC Platform and CPU Cores Page: 60
61 The Interrupt Controller is a single functional unit, which is located in a Cortex-A9 MPCore. G. Khan SoC Platform and CPU Cores Page: 61
62 GIC is responsible for centralizing all the interrupt sources before dispatching them to each individual Cortex-A9 processor core. There is one interrupt interface per Cortex- A9 processor core. The Interrupt Controller is memorymapped. The Cortex-A9 processors access it by using a private interface through the SCU. G. Khan SoC Platform and CPU Cores Page: 62
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