Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye

Transcription

1 Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink Robert Kaye 1

2 Agenda Once upon a time ARM designed systems Compute trends Bringing it all together with CoreLink 400 Series What s inside the box Coherency, virtualization, end-to-end QoS Compute sub-systems Any questions? 2

3 Once Upon a Time Over 20 Years Ago 3

4 Compute Trends Clients & the Cloud Personal computing in the post-smartphone era has changed everything Every screen is connected to the cloud Connected life with presence = my services must follow me Power budget want to do more within the same budget Software, security, camera as user interface, augmented reality What gets processed where is a function of bandwidth Technology implications: CPU/GPU/VPU throughput, memory sub-system, software programmer s model Hardware must be built to meet evolving software requirements 4

5 Bringing It All Together It s all about the system! Coherency, virtualization, non-blocking & hierarchical interconnect, power management, end-to-end QoS Software wants to see hardware as resources: Details e.g. registers pah! Want common API s e.g. OpenCL Software community want standardization of hardware resources Hardware assistance in the right place improves consistency & software portability system optimization is key and not just the CPU 5

6 ARM Easy to Select the Right System IP We call it the CoreLink 400 Series So lets take a closer look at what s inside the box Cache Coherent Interconnect CCI-400 Dual cluster CCI - 2 ACE/3 ACE-Lite ports, QVN, QoS, virtualization signalling, barriers, clock gating1 System IP for Cortex-A15 & Mali-T604 Cache Coherent Interconnect Coherent caches shared by processors & I/O AMBA 4 coherency extensions GIC-400 Mali-T604 Non-blocking virtual networks graphics New high efficiency Quad Quad Cortex-A15 Cortex-A15 memory controller 1/2/4 >90% interface utilization LPDDR2/DDR3 Product Name Headline Features System MMU for Hierarchical network interconnect, improved clock and Network Interconnect NIC-400 I/O virtualization Dynamic Memory Controller power management, AXI4 and APB4 support DMC-400 PHY PHY Quality of Service Enhanced bandwidth regulation Network Interconnect DDR3/LPDDR2 DDR3/LPDDR2 for SoC connectivity Thin Links Point-to-point packetization - reduce wiring congestion Reduced routing and power, end-to-end QoS QOS Virtual Networks Avoid cross-stream AND head-of-line blocking Compute subsystems designed and optimized by ARM I/O device Cache Coherent Interconnect CCI Series Network Interconnect NIC-400 Slaves Video Network Interconnect NIC-400 Slaves LCD Dynamic Memory Controller System Memory Management Generic Interrupt Controller DMC-400 GIC-400 QoS, virtual networks, LPDDR2/DDR3 smooth evolution to future memories e.g. WideIO Stage 2 memory translation, ARMv7 virtualization extensions compliant Share interrupts across clusters, ARM v7 virtualization extensions compliant 6

7 System IP for Cortex-A15 & Mali-T604 Cache Coherent Interconnect Coherent caches shared by processors & I/O AMBA 4 coherency extensions Non-blocking virtual networks New high efficiency memory controller 1/2/4 >90% interface utilization LPDDR2/DDR3 System MMU and GIC for virtualization Network Interconnect for SoC connectivity Quad Cortex-A15 GIC-400 Dynamic Memory Controller DMC-400 Cache Coherent Interconnect CCI-400 Reduced routing and power, end-to-end QoS Compute subsystems designed and optimized by ARM PHY DDR3/LPDDR2 Quad Cortex-A15 Mali-T604 graphics PHY DDR3/LPDDR2 400 Series I/O device Network Interconnect NIC-400 Slaves Video Network Interconnect NIC-400 Slaves LCD 7

8 Why Coherency? GIC-400 Quad Quad Cortex-A15 Cortex-A15 Mali-T604 graphics I/O device Video LCD Network Interconnect NIC-400 More processors & More shared data Increase in processor cores Increase in accelerator engines including multimedia, e.g. 3D Goal is more performance for less power Dynamic Memory Controller DMC-400 PHY DDR3/LPDDR2 Cache Coherent Interconnect CCI-400 PHY DDR3/LPDDR2 Network Interconnect NIC-400 Slaves Slaves Shared data needs to be managed ensure consistency Three ways to guarantee coherency of shared data Disable caching = lowest performance Software managed coherency = SW overhead for cache maintenance Hardware managed coherency = highest performance, scalable 8

9 New Applications Need Coherency OpenCL provides access to the vast processing power of Mali -T604 Applications include: Video editing and effects Camera & image processing (e.g. smile detection ) Image recognition (e.g. automotive lane detection) Gesture recognition systems Game engines (physics engines, particle physics) Photorealistic ray tracing And Artificial Intelligence 9

10 Hardware Coherency Past and Present ARM MPCore processors support scaling up to quad core SMP All processors see the same view of memory Performance scaling for applications Accelerator Coherence Port (ACP) allows sharing of MPCore caches Limited to one MPCore processor Bandwidth shared with processor interface Limited throughput Quad Cortex-A15 MPCore Cortex-A15 Cortex-A15 CoreLink CCI-400 Cache Coherent Interconnect Main Memory Cortex-A15 Cortex-A15 Integrated L2 cache Main Memory I/O Coherent Accelerator AMBA 4 System and I/O Bringing hardware coherency to the system AXI Coherency Extensions (ACE) CoreLink CCI-400 Cache Coherent Interconnect - enables scalable coherency Multiple processor clusters up to 8 Cortex -A15 cores Multiple accelerator engines with increased bandwidth 10

11 Reduce Your Cache Maintenance Costs Without hardware coherency, software must manage caches Flushing and invalidation of data requires many CPU cycles Data is written to main memory (DDR) This burns power, increases latency and occupies the CPU Cache maintenance software is notoriously difficult to debug AMBA 4 ACE allows hardware to manage cache coherency Caches do not need to be flushed or invalidated Processor can do useful work instead, or enter low power state External memory accesses are reduced No wasted cache flushing Shared data can now be read directly from processors caches! Hardware coherency simplifies software & processor spends less time maintaining caches good for power and performance 11

12 Why Virtualization? Virtualization: create multiple logical devices from one physical device Popek & Goldberg (1974) gave the requirements for virtualization Equivalence / Fidelity Underlying H/W is transparent to S/W Resource control / Safety System protection using sandboxing Efficiency / Performance Low overhead virtual machine Meeting these 3 requirements within the SoC is a key driver in the ARM world 12

13 Virtualization Everywhere Servers Widely used for consolidation of tasks on to CPUs Computing Enables multiple client OS, e.g. Windows on Linux Motorola Evoke QA4, world s first fully virtualized smartphone Common H/W view presented to S/W across product range Mainstream games consoles Implement virtual machines for legacy S/W Next gen STB and DTV hardware Sandboxing of user space to protect device firmware 13

14 Virtualization in Mobile and Embedded Innovation driving change (EETimes, April 2010) Low power processors now incorporate the same kind of hypervisor hardware acceleration enjoyed by desktop and server processors. Emerging virtualization uses Split mobile personalities Next generation mobile devices DTV with internet apps In-vehicle infotainment Gaming systems 2010/11 mobile & embedded design starts Including virtualization hardware support now 14

15 ARM Solution Cortex-A15, and GIC-400 ARM adds virtualization extensions standard to ARMv7 architecture in 2010 Cortex-A15 first processor with native hypervisor mode Mali-T604 GPU runs in virtual address space maps Mali accesses to physical address for the hypervisor virtualizes other masters GIC-400 virtualizes interrupts Virtual Address Space Physical Address Space Virtual Address Space Intermediate Physical Address Space 15

16 GIC-400 CoreLink and GIC-400 G I C Q u a d Q u a d C o r t e x - A 1 5 C o r t e x - A 1 5 M a l i - T g r a p h i c s M M U V i d e o L C D I / O d e v i c e Network Interconnect N I C M M U M M U Cache Coherent Interconnect C C I Dynamic Memory Controller D M C P H Y P H Y Network Interconnect N I C D D R 3 / L P D D R 2 D D R 3 / L P D D R 2 S l a v e s S l a v e s IO virtualization with distributed TLB maintenance messaging Stage 2 address translation for hypervisor support ARMv7 virtualization extension architecture compliant Generic Interrupt Controller for multiple Cortex-A15 clusters IRQs and FIQs securely managed by hypervisor for each OS ARMv7 virtualization extension architecture compliant 16

17 CoreLink Delivers Efficient Virtualization Equivalence / Fidelity Cortex-A15 processor works with and GIC-400 to present a virtual hardware view to S/W H/W can be upgraded as required without modifying S/W Resource control / Safety Hypervisor in complete control of the virtualized resources Cortex-A15, and GIC-400 sandbox each OS Efficiency / Performance Address translations are performed in hardware More efficient and simpler than para-virtualization No need to migrate device drivers into the hypervisor No need to trap and process IO accesses or interrupts Evidence from typical DMA test case: 1.5% overhead vs. 36% overhead for S/W only solution 17

18 Why End-to-End Quality of Service? Systems use external memory Higher data GB/s Higher frequency Contention for scarce bandwidth Engineering challenges Need low latency for CPU High bandwidth for GPU LCDC needs deterministic latency So what? Need common QoS scheme across interconnect & memory controller Maximise performance & power efficiency 18

19 End-to-End Quality of Service Interconnect Traffic regulation on entry Maximum bandwidth limits Outstanding transaction management Dynamic priority Uses QoS value in NIC-301, NIC-400 Changes priority to meet target latency Virtual Networks Remove blocking through system QoStraffic and latency regulation Video Engine CoreLink NIC-400 Memory Controller Scheduler aims for high memory efficiency whilst meeting QoS requirements Support for latency regulation and arbitration with QoS value Timeout mechanism for streaming and real-time traffic Separate read and write queues CoreLink DMC-400 Memory Controller Mali GPU CoreLink DMA-330 DRAM LCD Ctroller Cortex-A processor Peripheral Peripheral 19

20 SoC Energy Efficiency is a Function of Many cores high performance computing Energy efficient Cortex, Mali processors But significant % of energy used in the memory system, especially off-chip Efficient use of limited off-chip memory bandwidth DMC-400, >90% of max theoretical utilization CCI-400, NIC-400, QoS, QVN keep processors performing without compromising bandwidth utilization Higher cache utilization by software Coherency CCI-400 enables more on-chip accesses, less off-chip accesses Lowering power and raising performance! 20

21 Ease of use System PPA For software The ARM Compute Sub-System Common Cortex-A + Mali graphics and video platform For maximum software performance & availability CoreSight provides visibility For software debug and performance optimisation TrustZone and System MMU Hardware virtualisation to protect applications GPU CPU VE Cortex-A5/A8/A9/A15, Mali-55/200/400 MP, Mali-VE3/6 A range of scalable processing performance to fit your power & area budget CoreLink Network Interconnect and Dynamic Memory Controllers To maximise efficient use of shared main memory Verification and Performance Exploration (VPE) tool For early and rapid system design trade-off decisions AMBA Designer Fast and reliable IP configuration and sub-system assembly Example system designs for faster time to market Support & maintenance from a single quality IP provider 21

22 CoreLink 300 Series for AMBA 3 Raising SoC performance and power efficiency NIC-301 Network Interconnect Hierarchical design Advanced Quality of Service (QoS) for performance and latency Level 2 Cache Controller Increase CPU performance Reduce external memory accesses Dynamic Memory Controllers LPDDR2, DDR2 LPDDR, DDR, NVM Programmable DMA Controller Off load the CPU Multi-channel Mali -400 GPU Video CoreLink Network Interconnect NIC-301 switch AXI3 AXI3 128b QoS-301 AXI3 DMC-342 PHY AXI3 LPDDR2 Cortex-A9 CPU AXI3 AXI3 NIC-301 switch Other Periph L2C-310 AXI3 AXI3 64b QoS-301 Configurable AXI3/AHB/APB Other Periph AXI3 AXI3 DMA-330 Configurable AXI3/AHB NIC-301 switch AXI3 32b QoS-301 AXI3 NIC-301 switch Configurable AXI3/AHB/APB Other Periph NIC-301 top level hierarchy of switches Other Periph 22

23 Summary It s All About the System Coherency, virtualization, non-blocking & hierarchical interconnect, power management and end-to-end QoS Software wants to see hardware as resources Want common API s e.g. OpenCL Quad Cortex-A15 GIC-400 Quad Cortex-A15 Mali-T604 graphics 400 Series I/O device Cache Coherent Interconnect CCI-400 Video Network Interconnect NIC-400 LCD The software community want standardization of hardware resources Dynamic Memory Controller DMC-400 PHY PHY Network Interconnect NIC-400 DDR3/LPDDR2 DDR3/LPDDR2 Slaves Slaves Hardware assistance in the right place simplifies the software programmers view; improving consistency & software portability and reducing power consumption System optimization is key and not just the CPU 23

24 Thank You Please visit for ARM related technical details For any queries contact < > 24