Common PMD Interface Hari

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1 Common PMD Interface Hari HSSG November, 1999 Kauai, HI Nov 8, 1999 Page 1

2 Agenda Introduction Background Assumptions Chief Issues Guiding Decisions Interface cription High Speed Data I/F Management I/F Transceiver Support Generic Block Diagram Examples Power Down Modes Coding Proposal Functions/Features/Ru les Clock Tolerance Compensation Skew Budget kew Protocol Examples Usage Electrical Specs High Speed I/F Management I/F Timing Specs Jitter; Skew Summary Nov 8, 1999 Page 2

3 Hari History 1999 March 9-11: 10 Gigabit Ethernet Call for Interest; IEEE 802 Creates April - June: Various Industry Group Leaders (FC; NGIO; OIF) Express Interest in a Common 10 Gig PMD to HSSG Chair July 22: OIF Adopts Motion to Utilize 10 Gig Ethernet PHY for Future Low Cost Interconnect July 30: First Meeting of the Hari Group Oct 7: FC begins process for a 10 Gig Project Oct 26: Fifth and Final (?) Meeting Nov 8, 1999 Page 3

4 10 G Ethernet PHY Requirements HSSG has adopted these PHY related objectives: Family of Physical Layer specifications supporting links of: At least 100 m over installed MMF At least 300 m over MMF At least 2 km over SMF At least 10 km over SMF At least 40 km over SMF Support both LAN and WAN LAN at Gb/s data rate WAN at Gb/s data rate (SONET Friendly) A common MAC layer that supports both Nov 8, 1999 Page 4

5 Assumptions There will be multiple 10 Gig PHY/PMD solutions A single solution can t be ideal for all distance objectives There will be a PLL in the transceiver High speed media interface too fast for GBIC/1x9 style I/F The system I/F to the PMD can have relatively high jitter Architects desire >20 of trace between devices ire to physically separate optical transceiver from switch matrix Mitigate fan-out issues; Allow for greater flexibility igners desire a common interface PMD I/F Can t afford Vendor / PHY / PMD solution permutations ire fewest pins / highest speed signals reasonable ire for common transceiver usage across platforms (Ethernet, Fibre Channel, SIO, OIF...) Nov 8, 1999 Page 5

6 Chief Issues Addressed Support multiple protocols and encoding schema Support multiple optical PMD s WDM ial Parallel Multilevel Amplitude Layout, Timing, and Electrical Considerations Minimize Pin Count Skew compensation (include media) Electrical specifications Data will be self clocking; jitter specifications required Extension to wider interfaces Green power down modes Nov 8, 1999 Page 6

7 Guiding Decisions / Objectives Utilize 8B/10B Code Well understood; commonly used; minimal circuit overhead Relax Jitter requirements (the optics jitter budget is specified independent of Hari) Push Protocol Silicon to reasonable limit Future proof the architecture believed supportable as future pure CMOS core Support distances of 18 to 24 over FR4 Expect use of good design technique Use techniques that avoid unnecessary IP Avoid excessive penalties for specific PHY types Use self clocking data only Nov 8, 1999 Page 7

8 Data Format N x 8 bit 10 bit 1 bit 1 bit OSI Layer Stack Mapping Typical 1 Gig Link Protocol Coding SERDES XCVR Media OSI Ref. Application Presentation Session Transport Network Data Link Physical Proposed 10 Gig Link Protocol Coding SERDES SERDES XCVR Media 4 x 8 bit 4 x 10 bit Hari 4 x 1 bit 1 bit or 4 x 1 bit or 8 x 1 bit or? Nov 8, 1999 Page 8

9 Data Format GMII MDI 1 bit 1 bit OSI Mapping For Ethernet Typical 1 Gig Link MAC PCS PMA PMD Media OSI Ref. Application Presentation Session Transport Network Data Link Physical Proposed 10 Gig Link MAC PCS PMA? PMD Media XGMII MDI Hari 1 bit or 4 x 1 bit or 8 x 1 bit or? Nov 8, 1999 Page 9

10 Expanded Block Diagrams (Key) Transmit Receive P/S Protocol / Switch Sync Synchronization Pattern oder Insert / Delete Protocol / Switch kew Decoder Insert / Delete P/S Dsk ializer erializer (Bit/Byte Sync) Electrical to Optical C Optical to Electrical Coded Interface Nov 8, 1999 Page 10

11 Example: 1 Gig Partitions P/S C C O/E P/S C C Protocol Layers: MAC & PCS ; FC2 & FC B 10 1d Protocol with Integrated SERDES GLM 1d 1x9 GBIC 1x9 GBIC Nov 8, 1999 Page 11

12 Generic 10 Gig XCVR Data Flow O/E Not all blocks required by all transceivers Order of functional blocks may vary Some blocks may be trivial or share functions erializer and ializer probably share PLL might simply be a mux All Transceivers will require PLL & reclocking Character Insert/Delete needed to correct for clock variations Nov 8, 1999 Page 12

13 Generic Transceiver Local Clk PLL O/E Management Reference Clock and PLL are assumed necessary since Hari Interface has no jitter budget allocated to transceiver Management I/F covers all low speed functions like signal detect, transmit disable, fault, etc. Nov 8, 1999 Page 13

14 Transceiver Functional Comparison Transceiver Type Transmit Receive Common Tx & Rx & assumed if is implemented (due to buffer) Implementations with clocks are reserved in case jitter on media can only be maintained with a local PMD clock. 12.5G ial a a a a a a a a a a 4X WWDM a a a a a a 4X Parallel a a a a a a Multilevel a a a a a a a a a a a a a a 10G ial a a a a a a a a a a a a a a a 12.5G ial a a a a a a a a a a a a a 4 x WWDM a a a a a a a a a a a 4 x Parallel a a a a a a a a a a a Multilevel a a a a a a a a a a a a a a a a a O/E Clk PLL Mgmt Nov 8, 1999 Page 14

15 Power Down Domains Ref Clk PLL O/E Management 0: Management Always On; Everything else off 1: 0 + Preamp/Postamp/Signal Detect On -- watch for incoming light 2: All But Laser -- Support EWRAP (PLL running for Rx quick sync) 3: Reserved 4: Everything On -- Full function Nov 8, 1999 Page 15

16 10.0 Gb/s ial Transceiver Local Clk PLL O/E Management Assumed Use of Scrambled Code Transform complexity is determined by protocol requirements of the serialized stream (e.g. SONET) Nov 8, 1999 Page 16

17 12.5 Gb/s ial Transceiver Local Clk PLL O/E Management Assumed use of 8B/10B Code throughout No ode / Decode Blocks Required : Transform could be a simple disparity correction Nov 8, 1999 Page 17

18 4 x WWDM and Parallel Local Clk PLL O/E Management Assumed use of 8B/10B Code throughout No ode / Decode or Transform Blocks Required SERDES assumed when SID buffer done in parallel Nov 8, 1999 Page 18

19 Retimed 4 x WWDM/Parallel SKIP Local Clk PLL SKIP O/E Management Most effective solution for WWDM and Parallel if local clock is not required and PHY can meet jitter requirements. Nov 8, 1999 Page 19

20 Multilevel Transceiver (e.g. PAM) Local Clk PLL O/E Management Will use all functional blocks, with the exception that the ode/decode and ializer functions will be substituted with magic analog sauce. Nov 8, 1999 Page 20

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