Handling Challenges of Multi-Core Technology in Automotive Software Engineering

Transcription

1 Model Based Development Tools for Embedded Multi-Core Systems Handling Challenges of Multi-Core Technology in Automotive Software Engineering VECTOR INDIA CONFERENCE 2017 Timing-Architects Embedded Systems GmbH Dr.-Ing. Michael Deubzer, CEO 18 July 2017

2 Agenda Multi-Core Technology in Automotive Systems Multi-Core Technology Challenges Timing Aspects in Multi-Core Systems A Model-Based Approach for Multi-Core Systems Verifying Timing in Multi-Core Systems Conclusion 2

3 Multi-core Technology in Automotive Systems 3

4 Multi-core Technology in Automotive Systems Increased Demand for Processing Capacity in Automotive Systems Zero Emission Autonomous Driving Car2x Interconnection 4

5 Multi-Core Technology in Automotive Systems Why multi-core gets standard Kurzweil, Ray; The Singularity Is Near; Viking, New York;

6 Multi-Core Technology in Automotive Systems New E/E Architecture for High-Performance Multi-core Systems ECU Gateway Engine ECU PT ECU PT ECU PT ECU PT ECU PT ECU PT Braking ECU CH ECU CH ECU CH ECU CH ECU CH ECU CH ECU B ECU B ECU B ECU B ECU B ECU Front Steering ECU Right ECU Performance Unit ECU Real-Time Unit Braking ECU Back ECU PT ECU PT ECU CH ECU CH Engine ECU Left ECU PT ECU PT Steering Today E/E Architecture Domain clusters with interconnected single-core ECUs One ECU per functional unit Possible Future E/E Architecture High-performance domain multicore ECUs Real-time ECUs for actuator control Integration of multiple functional units one ECU 6

7 Multi-core Technology Challenges 7

8 Multi-Core Technology Challenges Influencing Factors from Processor Hardware Single-Core Multi-Core Core 1 Core 1 Core 2 Core n L1 Cache L1 Cache L1 Cache L1 Cache Timer Unit RAM RAM 1 ROM 1 RAM 1 ROM 1 RAM n ROM n Bus Crossbar FLASH RAM 0 FLASH DMA Controller Timer Unit Sequential execution on one processing unit Single memory Single resource Allocating application on multiple processing units Allocating data on available memory modules Synchronizing access to memory and peripherals 8

9 Multi-core Technology Challenges Managing Data Exchange Across Application Software Task A Task B Core 1 Task A #1 #2 0x01 0x02 0x03 Mem 1 Task B # 1 # 2 Core 1 Task A 0x01 Core 1 Task C Core 2 Task C Core 2 Task B Core 2 Data Consistency Data Coherency Data Stability 9

10 Multi-Core Technology Challenges Partitioning of Application Software Impacts of Partitioning Data-dependencies across Runnables Frequency of data-exchange Latency constraint on data-exchange Braking Software Braking RE_B1 Diagnosis RE_D1 Control RE_C1 Execution sequence constraint Allocation constraint RE_B2 RE_B3 RE_B4 RE_D2 RE_D3 RE_C2 RE_C3 Core 1 Core 2 Core 3 Core 4 10

11 Timing Aspects in Multi-Core Systems 11

12 Timing Aspects in Multi-Core Systems 12

13 Timing Aspects in Multi-Core Systems Timing Requirements on System Level t = < 60.0 ms t = < ms t = < ms t = < 50.0 ms End-to-end timing behavior requirement for the distributed system SW Architecture Sensor RE Fusion RE Braking RE Legend SWC SW Component RE Runnable Entity In- / Output Sensor ECU Fusion ECU Braking ECU Event-Chain Network / Communication HW Architecture 13

14 Timing Aspects in Multi-Core Systems Timing Requirements on ECU Level Static View Braking Software t = < 50.0 ms Braking Braking RE_B1 RE_B2 RE_B3 RE_B4 Diagnosis RE_D1 RE_D2 RE_D3 Control RE_C1 RE_C2 RE_C3 Task 1ms Task 4ms Task 10ms RE Task 20ms Dynamic View t = < 50.0 ms Braking ECU 1ms 10ms 4ms RE_B1 RE_B1 RE_B1 RE_B2 RE_B3 RE_B4 RE_D1 RE_D2 RE_C1 20ms RE_C2 RE_C3 RE_D3 14

15 2nd/3rd Level Top Level Task Level Timing Aspects in Multi-Core Systems Parallelization Concepts Task Level Parallelism Task A Task B Task C Runnable (Top) Level Parallelism Task C-1 Task C-2 Service/Algorithm Level Parallelism Runnable Core 1 Core 2 Core 1 Core 2 Core 1 Core 2 Core 3 By change of Configuration + Less synchronization overhead + Less context switching overhead + No change of runnable execution sequence - No speedup in function execution - Low load balancing capabilities By change of Integration + Better load balancing capabilities + Reduction of task response times - Analysis of dataflow necessary - Creation of new tasks necessary By change of Implementation + Highest potential of load balancing + Reduction of function execution times (Speedup) - High synchronization effort - Modification of source-code 15

16 Timing Aspects in Multi-Core Systems Scheduling Concepts Event-based Scheduling Events Events Time-Triggered Scheduling T3 T2 T2 T1 T1 Time T1 T2 T3 Time Runtime decision on task execution Design-time decision on task execution Pro: Fast reaction on interrupts Con: Scheduling overhead Jitter for low priority task High Interferences at parallel resource access Pro: Low/(no) jitter for tasks Con: Lower maximal system utilization due to worstcase assumptions Longer reaction times 16

17 Timing Aspects in Multi-Core Systems Communication Concepts Single-Core Approach RE_B1 RE_B2 RE_B3 RE_B4 RE_B1 RE_D1 RE_D2 RE_C1 Global Shared Memory Non Data-protected Approach Data-protected Approach RE_B1 RE_B1 Core 1 RE_B1 RE_B1 Core 1 Global Shared Memory Global Shared Memory RE_B2 RE_B3 RE_B4 RE_D1 RE_D2 RE_C1 Core 2 RE_B2 RE_B3 RE_B4 RE_D1 RE_D2 RE_C1 Core 2 17

18 Timing Aspects in Multi-Core Systems Timing-Behavior in Single-Core System 1ms RE_B1 RE_B1 RE_B1 10ms 4ms 20ms RE_B2 RE_B3 RE_B4 RE_D1 RE_D2 RE_C1 RE_C2 RE_C3 RE_D3 Timing-Behavior in Multi-Core System 1ms 10ms 4ms 20ms RE_B1 RE_B1 RE_B1 RE_D1 RE_D2 RE_C1 RE_D1 RE_D2 RE_C1 RE_B2 RE_B3 RE_B4 RE_C2 RE_C3 RE_D3 Core 1 Core 2 18

19 Timing Aspects in Multi-Core Systems Improving Timing Behavior of Multi-Core Systems Change of Runnable Execution Sequence 1ms 10ms 4ms 20ms RE_B1 RE_B1 RE_B1 RE_D1 RE_D2 RE_C1 RE_D1 RE_D2 RE_C1 RE_B2 RE_B3 RE_B4 RE_C2 RE_C3 RE_D3 Core 1 Core 2 Earlier Buffer export / Later Buffer update Re-Allocation of Task to other Core 19

20 A Model-Based Approach for Multi-Core Systems 20

21 A Model-Based Approach for Multi-Core Systems RE_B1 1. Data Acquisition Data Dependency Analysis RE_B2 RE_B3 RE_D1 RE_D2 2. Partitioning Grouping of Functions to Time Groups (based on Sequence Needs & Event-Chains) RE_B2 RE_B1 RE_B3 RE_D1 RE_D2 3. Integration Positioning of Functions into Sequences Allocation of Tasks to Cores (OS Partitions) RE_B2 RE_B3 RE_D2 Core 1 Core 2 4. Communication Interfaces Analysis of Data Consistency / Coherency / Stability Calculation of Communication Buffers / RTE Configuration RE_B2 RE_B3 5. Code Generation Runnable Call Tree Buffering Routines RE_B2 RE_B3 21

22 A Model-Based Approach for Multi-Core Systems Workflow on System Modeling System Modeling Timing Simulation 22

23 Software Function II Software Function I A Model-Based Approach for Multi-Core Systems Collaboration Model between OEM & TIER1 OEM Functions Data-flow Execution Order TIER 1 Tasks Functions Data-flow Handling Projects with Multiple Application Software Providers Integration of application software on model-based data Global optimization of complete application Export of Integration configuration Integrated System Execution Order Model Merge (OS Data) (Function Runtimes) 23

24 A Model-Based Approach for Multi-Core Systems DaVinci Developer 1 2 SWC Description 4 *.ARXML DaVinci Configurator ECU Configuration *.ARXML TA Tool Suite 5 Improvement of an existing system: Project configuration with DaVinci Tools Exporting ECU Configuration and System Description Import into TA Tool Suite Timing analysis in TA Simulator Optimization in TA Optimizer Update of ECU Configuration 25

25 Verifying Timing in Multi-Core Systems 29

26 Verifying Timing in Multi-Core Systems Closing the Development Cycle Schedule Analysis Timing Requirements Runtime Measurements System Model Metrics Target Platform Metric Analysis Metrics Simulation Module Test Recorded Trace 30

27 Verifying Timing in Multi-Core Systems Trace Export Tracing TA Tool Suite SWC Description ECU *.ARXML Configuration Code Generation / Flashing ECU Configuration *.ARXML *.ARXML Post-Optimization-Verification Importing ECU-C update into DaVinci Code generation, flashing and tracing equal to initial verification DaVinci ToolChain Validation of updated project and comparison to simulation results in TA Inspector 31

28 Outlook on Multi-Core Systems 32

29 Outlook on Multi-Core Systems Improving efficiency and predictability by mixed timetriggered and event-triggered scheduling Integration of applications from different domains with different buffering and scheduling strategies Introducing increased dynamic behavior in scheduling and communication with Adaptive AUTOSAR by dynamic task allocation and service-oriented communication 33

30 THANK YOU FOR YOUR ATTENTION! Timing-Architects Embedded Systems GmbH Phone: +49 (0) Franz-Mayer-Straße 1 Fax: +49 (0) Regensburg info@timing-architects.com