Veloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics

Size: px
Start display at page:

Download "Veloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics"

Transcription

1 Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics

2 Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2

3 Veloce Emulation Use Modes Solutions portfolios address all use modes isolve solutions In Circuit Emulation Simulation Acceleration VIP /Transactors VirtuaLAB and Memories Virtual Lab Emulation Software Debug JTAG, Virtual Probe, Veloce Codelink One Platform All use modes 3

4 Veloce Delivers Real Value Design: Network switch with multiple 10G ports Mode: Streaming 64-byte packets on all ports Simulation ~1/4th frame/sec Vs Emulation ~3,662 frames/sec ~15,000x faster than simulation Billions of transactions across all Ethernet ports 4

5 Crystal2 Custom Architecture Rich interconnect yields 5 minute chip compiles Built-in logic analyzer all signals visible all of the time Custom Virtual Wires logic for reliable chip-to-chip routing Switched backplane interconnect for board-to-board routing Fully automated software to compile designs Crystal2 Advanced Logic Board Veloce2 Quattro Full custom IC 5

6 Maximus: Enterprise Verification Platform AVB Up to 64 Capacity (user gates) Up to 1Billion ICE users Up to 16 TBX or stand alone users Up to 64 Physical IOs Up to 9600 (120*80) Extended IO Power Noise Level Up to 4X 50 kw 75 dba 6

7 Veloce OS3 Enterprise Server Consolidates global Veloce resources into a unified high-capacity entity Speeds high-priority jobs by suspending jobs of low priority Shields emulator complexity from LSF and Netbatch queue managers Automatically adapts to change in HW availability 7

8 Veloce Enables Full Chip Validation The confidence level in the design before tape-out is maximized with full chip emulation System level architectural bugs detection such as Performance, HW-SW tests, Interrupts, Cache configuration, Memory Coherency, interconnect, and others Verifying the integration: interconnect, memory map, clocks, reset sequences Real life HW-SW test cases on OS create sequences that get to corner cases almost impossible to reach in sub-system clusters. Power aware verification. Measuring power metrics is best done with real SW in full chip Verifying different power modes Verifying power with real OS task-switching effects 8

9 Full-Chip Validation Prior to Silicon: Boot OS, Drivers Validation OS and device drivers run on RTL or ISS processor models VirtuaLAB peripherals exercise interfaces SW debug solutions Power analysis Codelink Multi-core SW/HW debug SoC PHY PHY PHY PHY CPU USB Ethernet SATA Display Processor Master IF SlaveIF Slave IF Slave IF Slave IF Arbiter Master IF CPU Master IF Software Memory Fabric Slave IF UART Slave IF GPIO Fabric PCI Express PHY 9

10 Veloce Peripheral Interface Solutions Identical IP used for all solution offerings Peripheral Interface Design IP Silicon proven Example Test Suite Coverag e and Assertio ns Test Plan Users Test Sequences Accelerated Transactor Users DUT isolve Physical Peripherals VirtuaLAB Virtual Peripherals Verification IP Protocol Transactors 10

11 Advantages of VirtuaLAB ROI Attractive alternative to ICE Ideal for multi-user and multi-project Quality VirtuaLAB runs on Linux host Peripherals are hardware accurate Productivity Instantly reconfigured Datacenter compatible 11

12 Off-line HW/SW Co-Debug with Codelink Waveform View SW Debugger Many Off-Line Execution Data Bases 12 Many Software Engineers at the same time

13 ARM Case Study 13

14 14

15 15

16 16

17 17

18 18

19 19

20 Going Beyond Simulation Acceleration Simulation Acceleration OVM/UVM SystemVerilog C/SystemC Accelerated Transactors SW Debug Codelink VProbe Warpcore QEMU Software Debug Virtual Protocol Solutions USB SATA Video Ethernet VirtuaLAB Solutions PCIe Testbench Xpress Co-Model Channels Physical Protocol Solutions PCIe SATA Video USB Ethernet... Physical I/O isolve Solutions 20

21 21

The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System

The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System Laurent VUILLEMIN Platform Compile Software Manager Emulation Division Agenda What is

More information

Strato and Strato OS. Justin Zhang Senior Applications Engineering Manager. Your new weapon for verification challenge. Nov 2017

Strato and Strato OS. Justin Zhang Senior Applications Engineering Manager. Your new weapon for verification challenge. Nov 2017 Strato and Strato OS Your new weapon for verification challenge Justin Zhang Senior Applications Engineering Manager Nov 2017 Emulation Market Evolution Emulation moved to Virtualization with Veloce2 Data

More information

Validation Strategies with pre-silicon platforms

Validation Strategies with pre-silicon platforms Validation Strategies with pre-silicon platforms Shantanu Ganguly Synopsys Inc April 10 2014 2014 Synopsys. All rights reserved. 1 Agenda Market Trends Emulation HW Considerations Emulation Scenarios Debug

More information

Software Driven Verification at SoC Level. Perspec System Verifier Overview

Software Driven Verification at SoC Level. Perspec System Verifier Overview Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015 IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to

More information

Does FPGA-based prototyping really have to be this difficult?

Does FPGA-based prototyping really have to be this difficult? Does FPGA-based prototyping really have to be this difficult? Embedded Conference Finland Andrew Marshall May 2017 What is FPGA-Based Prototyping? Primary platform for pre-silicon software development

More information

Tutorial M02. Software Debug on ARM Processors in Emulation. March 24, 2014

Tutorial M02. Software Debug on ARM Processors in Emulation. March 24, 2014 Tutorial M02 Software Debug on ARM Processors in Emulation Tutorials Chair Franco Fummi - Università di Verona Italy March 24, 2014 Fill in, please, the tutorial evaluation form, available on the conference

More information

Yafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces

Yafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces Yafit Snir Arindam Guha, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and

More information

Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface

Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface Thierry Berdah, Yafit Snir Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface Agenda Typical Verification Challenges of MIPI CSI-2 SM designs IP, Sub System

More information

Figure 1: Target environment includes peripherals.

Figure 1: Target environment includes peripherals. Virtualization Delivers Total Verification of SoC Hardware, Software, and Interfaces by Jim Kenney, Marketing Director, Emulation Division, Mentor Graphics With the majority of designs today containing

More information

Test and Verification Solutions. ARM Based SOC Design and Verification

Test and Verification Solutions. ARM Based SOC Design and Verification Test and Verification Solutions ARM Based SOC Design and Verification 7 July 2008 1 7 July 2008 14 March 2 Agenda System Verification Challenges ARM SoC DV Methodology ARM SoC Test bench Construction Conclusion

More information

Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015

Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015 Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs August 2015 SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal Software DSP Software Bare Metal Software

More information

Designing with ALTERA SoC Hardware

Designing with ALTERA SoC Hardware Designing with ALTERA SoC Hardware Course Description This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software. The course combines 60% theory

More information

Optimizing Emulator Utilization by Russ Klein, Program Director, Mentor Graphics

Optimizing Emulator Utilization by Russ Klein, Program Director, Mentor Graphics Optimizing Emulator Utilization by Russ Klein, Program Director, Mentor Graphics INTRODUCTION Emulators, like Mentor Graphics Veloce, are able to run designs in RTL orders of magnitude faster than logic

More information

Verification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems

Verification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems Verification Futures 2016 Nick Heaton, Distinguished Engineer, Cadence Systems Agenda Update on Challenges presented in 2015, namely Scalability of the verification engines The rise of Use-Case Driven

More information

Graph-Based Verification in a UVM Environment

Graph-Based Verification in a UVM Environment Graph-Based Verification in a UVM Environment Staffan Berg European Applications Engineer July 2012 Graph-Based Intelligent Testbench Automation (itba) Welcome DVClub Attendees Organizers Presenters Verification

More information

Accelerating Networking Products to Market by Lauro Rizzatti, Rizzatti LLC

Accelerating Networking Products to Market by Lauro Rizzatti, Rizzatti LLC Accelerating Networking Products to Market by Lauro Rizzatti, Rizzatti LLC Take a step down the stack beyond optical networks, switches, routers and software-defined networking to consider the networking

More information

Verification Futures The next three years. February 2015 Nick Heaton, Distinguished Engineer

Verification Futures The next three years. February 2015 Nick Heaton, Distinguished Engineer Verification Futures The next three years February 2015 Nick Heaton, Distinguished Engineer Let s rewind to November 2011 2 2014 Cadence Design Systems, Inc. All rights reserved. November 2011 SoC Integration

More information

ZeBu : A Unified Verification Approach for Hardware Designers and Embedded Software Developers

ZeBu : A Unified Verification Approach for Hardware Designers and Embedded Software Developers THE FASTEST VERIFICATION ZeBu : A Unified Verification Approach for Hardware Designers and Embedded Software Developers White Paper April, 2010 www.eve-team.com Introduction Moore s law continues to drive

More information

Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World

Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World I N V E N T I V E Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World Frank Schirrmeister, Steve Brown, Larry Melling (Cadence) Dave Beal (Xilinx) Agenda Virtual Platforms Xilinx

More information

Will Everything Start To Look Like An SoC?

Will Everything Start To Look Like An SoC? Will Everything Start To Look Like An SoC? Vikas Gautam, Synopsys Verification Futures Conference 2013 Bangalore, India March 2013 Synopsys 2012 1 SystemVerilog Inherits the Earth e erm SV urm AVM 1.0/2.0/3.0

More information

Early Software Development Through Emulation for a Complex SoC

Early Software Development Through Emulation for a Complex SoC Early Software Development Through Emulation for a Complex SoC FTF-NET-F0204 Raghav U. Nayak Senior Validation Engineer A P R. 2 0 1 4 TM External Use Session Objectives After completing this session you

More information

100M Gate Designs in FPGAs

100M Gate Designs in FPGAs 100M Gate Designs in FPGAs Fact or Fiction? NMI FPGA Network 11 th October 2016 Jonathan Meadowcroft, Cadence Design Systems Why in the world, would I do that? ASIC replacement? Probably not! Cost prohibitive

More information

Verifying big.little using the Palladium XP. Deepak Venkatesan Murtaza Johar ARM India

Verifying big.little using the Palladium XP. Deepak Venkatesan Murtaza Johar ARM India Verifying big.little using the Palladium XP Deepak Venkatesan Murtaza Johar ARM India 1 Agenda PART 1 big.little overview What is big.little? ARM Functional verification methodology System Validation System

More information

NS115 System Emulation Based on Cadence Palladium XP

NS115 System Emulation Based on Cadence Palladium XP NS115 System Emulation Based on Cadence Palladium XP wangpeng 新岸线 NUFRONT Agenda Background and Challenges Porting ASIC to Palladium XP Software Environment Co Verification and Power Analysis Summary Background

More information

Designing with ALTERA SoC

Designing with ALTERA SoC Designing with ALTERA SoC תיאורהקורס קורסזהמספקאתכלהידע התיאורטיוהמעשילתכנוןרכיביSoC שלחברתALTERA תחתסביבת הפיתוחII.Quartus הקורסמשלב 60% תיאוריהו- 40% עבודה מעשית עללוחותפיתוח.SoC הקורסמתחילבסקירתמשפחותרכבי

More information

Fujitsu SOC Fujitsu Microelectronics America, Inc.

Fujitsu SOC Fujitsu Microelectronics America, Inc. Fujitsu SOC 1 Overview Fujitsu SOC The Fujitsu Advantage Fujitsu Solution Platform IPWare Library Example of SOC Engagement Model Methodology and Tools 2 SDRAM Raptor AHB IP Controller Flas h DM A Controller

More information

System-on-Chip Architecture for Mobile Applications. Sabyasachi Dey

System-on-Chip Architecture for Mobile Applications. Sabyasachi Dey System-on-Chip Architecture for Mobile Applications Sabyasachi Dey Email: sabyasachi.dey@gmail.com Agenda What is Mobile Application Platform Challenges Key Architecture Focus Areas Conclusion Mobile Revolution

More information

Will Everything Start To Look Like An SoC?

Will Everything Start To Look Like An SoC? Will Everything Start To Look Like An SoC? Janick Bergeron, Synopsys Verification Futures Conference 2012 France, Germany, UK November 2012 Synopsys 2012 1 SystemVerilog Inherits the Earth e erm SV urm

More information

The Challenges of System Design. Raising Performance and Reducing Power Consumption

The Challenges of System Design. Raising Performance and Reducing Power Consumption The Challenges of System Design Raising Performance and Reducing Power Consumption 1 Agenda The key challenges Visibility for software optimisation Efficiency for improved PPA 2 Product Challenge - Software

More information

Assembling and Debugging VPs of Complex Cycle Accurate Multicore Systems. July 2009

Assembling and Debugging VPs of Complex Cycle Accurate Multicore Systems. July 2009 Assembling and Debugging VPs of Complex Cycle Accurate Multicore Systems July 2009 Model Requirements in a Virtual Platform Control initialization, breakpoints, etc Visibility PV registers, memories, profiling

More information

Embedded HW/SW Co-Development

Embedded HW/SW Co-Development Embedded HW/SW Co-Development It May be Driven by the Hardware Stupid! Frank Schirrmeister EDPS 2013 Monterey April 18th SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal

More information

RISC-V based core as a soft processor in FPGAs Chowdhary Musunuri Sr. Director, Solutions & Applications Microsemi

RISC-V based core as a soft processor in FPGAs Chowdhary Musunuri Sr. Director, Solutions & Applications Microsemi Power Matters. TM RISC-V based core as a soft processor in FPGAs Chowdhary Musunuri Sr. Director, Solutions & Applications Microsemi chowdhary.musunuri@microsemi.com RIC217 1 Agenda A brief introduction

More information

Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models. Jason Andrews

Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models. Jason Andrews Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models Jason Andrews Agenda System Performance Analysis IP Configuration System Creation Methodology: Create,

More information

Creating hybrid FPGA/virtual platform prototypes

Creating hybrid FPGA/virtual platform prototypes Creating hybrid FPGA/virtual platform prototypes Know how to use the PCIe-over-Cabling interface in its HAPS-60-based system to create a new class of hybrid prototypes. By Troy Scott Product Marketing

More information

Combining Arm & RISC-V in Heterogeneous Designs

Combining Arm & RISC-V in Heterogeneous Designs Combining Arm & RISC-V in Heterogeneous Designs Gajinder Panesar, CTO, UltraSoC gajinder.panesar@ultrasoc.com RISC-V Summit 3 5 December 2018 Santa Clara, USA Problem statement Deterministic multi-core

More information

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes Presented at Design Automation Conference (DAC) San Francisco, CA, June 4, 2012. Presented by Chuck Cruse FPGA Hardware

More information

ARM Processors for Embedded Applications

ARM Processors for Embedded Applications ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or

More information

Functional Verification of the SiCortex Multiprocessor System-on-a-Chip. Oleg Petlin, Wilson Snyder

Functional Verification of the SiCortex Multiprocessor System-on-a-Chip. Oleg Petlin, Wilson Snyder Functional Verification of the SiCortex Multiprocessor System-on-a-Chip Oleg Petlin, Wilson Snyder wsnyder@wsnyder.org June 7, 2007 Agenda What we ve built Verification challenges Verification productivity

More information

WHICH MICRO? What does MCU needs to do in my system? What are the tasks? Dr. Adriana Becker-Gomez

WHICH MICRO? What does MCU needs to do in my system? What are the tasks? Dr. Adriana Becker-Gomez 1 WHICH MICRO? What does MCU needs to do in my system? What are the tasks? Dr. Adriana Becker-Gomez Email: axbeec@rit.edu Office: 9-3477 2 Specs System design: High level definition (functional specs)

More information

Using Formalized Programming Sequences for Higher Quality Virtual Prototypes

Using Formalized Programming Sequences for Higher Quality Virtual Prototypes Using Formalized Programming Sequences for Higher Quality Virtual Prototypes Sean Boylan Duolog Technologies Outline Motivation - VSP Quality Programming Sequences Applying Sequences Tools for Sequences

More information

ESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer)

ESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer) ESE Back End 2.0 D. Gajski, S. Abdi (with contributions from H. Cho, D. Shin, A. Gerstlauer) Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu 1 Technology advantages

More information

Multi-core microcontroller design with Cortex-M processors and CoreSight SoC

Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Joseph Yiu, ARM Ian Johnson, ARM January 2013 Abstract: While the majority of Cortex -M processor-based microcontrollers are

More information

Effective System Design with ARM System IP

Effective System Design with ARM System IP Effective System Design with ARM System IP Mentor Technical Forum 2009 Serge Poublan Product Marketing Manager ARM 1 Higher level of integration WiFi Platform OS Graphic 13 days standby Bluetooth MP3 Camera

More information

Assertion Based Verification of AMBA-AHB Using System Verilog

Assertion Based Verification of AMBA-AHB Using System Verilog Assertion Based Verification of AMBA-AHB Using System Verilog N.Karthik M.Tech VLSI, CMR Institute of Technology, Kandlakoya Village, Medchal Road, Hyderabad, Telangana 501401. M.Gurunadha Babu Professor

More information

Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02

Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02 Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC

More information

Zynq-7000 All Programmable SoC Product Overview

Zynq-7000 All Programmable SoC Product Overview Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform

More information

The How To s of Metric Driven Verification to Maximize Productivity

The How To s of Metric Driven Verification to Maximize Productivity The How To s of Metric Driven Verification to Maximize Productivity Author/Prensenter: Matt Graham Author: John Brennan Cadence Design Systems, Inc. Accellera Systems Initiative 1 The How To s of Metric

More information

Designing Embedded Processors in FPGAs

Designing Embedded Processors in FPGAs Designing Embedded Processors in FPGAs 2002 Agenda Industrial Control Systems Concept Implementation Summary & Conclusions Industrial Control Systems Typically Low Volume Many Variations Required High

More information

Introduction to the Qsys System Integration Tool

Introduction to the Qsys System Integration Tool Introduction to the Qsys System Integration Tool Course Description This course will teach you how to quickly build designs for Altera FPGAs using Altera s Qsys system-level integration tool. You will

More information

Formal for Everyone Challenges in Achievable Multicore Design and Verification. FMCAD 25 Oct 2012 Daryl Stewart

Formal for Everyone Challenges in Achievable Multicore Design and Verification. FMCAD 25 Oct 2012 Daryl Stewart Formal for Everyone Challenges in Achievable Multicore Design and Verification FMCAD 25 Oct 2012 Daryl Stewart 1 ARM is an IP company ARM licenses technology to a network of more than 1000 partner companies

More information

Shortest path to the lab. Real-world verification. Probes provide observability

Shortest path to the lab. Real-world verification. Probes provide observability OVM/UVM for FPGAs: The End of Burn and Churn FPGA Verification by In-Circuit Test Burn and churn based on at-speed test with real input 2 Shortest path to the lab Nominal simulation of RTL blocks Relatively

More information

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology) 1 Introduction............................................... 1 1.1 Functional Design Verification: Current State of Affair......... 2 1.2 Where Are the Bugs?.................................... 3 2 Functional

More information

Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components

Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components By William Orme, Strategic Marketing Manager, ARM Ltd. and Nick Heaton, Senior Solutions Architect, Cadence Finding

More information

FPQ6 - MPC8313E implementation

FPQ6 - MPC8313E implementation Formation MPC8313E implementation: This course covers PowerQUICC II Pro MPC8313 - Processeurs PowerPC: NXP Power CPUs FPQ6 - MPC8313E implementation This course covers PowerQUICC II Pro MPC8313 Objectives

More information

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus.

The Embedded computing platform. Four-cycle handshake. Bus protocol. Typical bus signals. Four-cycle example. CPU bus. The Embedded computing platform CPU bus. Memory. I/O devices. CPU bus Connects CPU to: memory; devices. Protocol controls communication between entities. Bus protocol Determines who gets to use the bus

More information

ECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego

ECE 111 ECE 111. Advanced Digital Design. Advanced Digital Design Winter, Sujit Dey. Sujit Dey. ECE Department UC San Diego Advanced Digital Winter, 2009 ECE Department UC San Diego dey@ece.ucsd.edu http://esdat.ucsd.edu Winter 2009 Advanced Digital Objective: of a hardware-software embedded system using advanced design methodologies

More information

ARM SERVER STANDARDIZATION

ARM SERVER STANDARDIZATION ARM SERVER STANDARDIZATION (and a general update on some happenings at Red Hat) Jon Masters, Chief ARM Architect, Red Hat 6+ YEARS OF ARM AT RED HAT Red Hat ARM Team formed in March 2011 Bootstrapped ARMv8

More information

Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye

Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink. Robert Kaye Building High Performance, Power Efficient Cortex and Mali systems with ARM CoreLink Robert Kaye 1 Agenda Once upon a time ARM designed systems Compute trends Bringing it all together with CoreLink 400

More information

DEVELOPMENT AND VERIFICATION OF AHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE

DEVELOPMENT AND VERIFICATION OF AHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE DEVELOPMENT AND VERIFICATION OF AHB2APB BRIDGE PROTOCOL USING UVM TECHNIQUE N.G.N.PRASAD Assistant Professor K.I.E.T College, Korangi Abstract: The AMBA AHB is for high-performance, high clock frequency

More information

High Speed Multi-User ASIC/SoC Prototyping system

High Speed Multi-User ASIC/SoC Prototyping system High Speed Multi-User ASIC/SoC Prototyping system Technical Resource Document Date: August 23, 2010 About GiDEL GiDEL has become one of the market leaders as a company that continuously provides cuttingedge

More information

Qsys and IP Core Integration

Qsys and IP Core Integration Qsys and IP Core Integration Stephen A. Edwards (after David Lariviere) Columbia University Spring 2016 IP Cores Altera s IP Core Integration Tools Connecting IP Cores IP Cores Cyclone V SoC: A Mix of

More information

Responding to TAT Improvement Challenge through Testbench Configurability and Re-use

Responding to TAT Improvement Challenge through Testbench Configurability and Re-use Responding to TAT Improvement Challenge through Testbench Configurability and Re-use Akhila M, Kartik Jain, Renuka Devi, Mukesh Bhartiya Accellera Systems Initiative 1 Motivation Agenda Generic AMBA based

More information

Designing with Nios II Processor for Hardware Engineers

Designing with Nios II Processor for Hardware Engineers Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under

More information

Speeding AM335x Programmable Realtime Unit (PRU) Application Development Through Improved Debug Tools

Speeding AM335x Programmable Realtime Unit (PRU) Application Development Through Improved Debug Tools Speeding AM335x Programmable Realtime Unit (PRU) Application Development Through Improved Debug Tools The hardware modules and descriptions referred to in this document are *NOT SUPPORTED* by Texas Instruments

More information

Break Your SoC with Automatically Generated C Test Cases

Break Your SoC with Automatically Generated C Test Cases Break Your SoC with Automatically Generated C Test Cases Frederic Krampac Senior Applications Engineer Breker Verification Systems, Inc. The Myths of SoC Verification The IPs are well verified the SoC

More information

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide by Prashant Dixit, Questa VIP Product Team, Mentor Graphics

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide by Prashant Dixit, Questa VIP Product Team, Mentor Graphics Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide by Prashant Dixit, Questa VIP Product Team, Mentor Graphics ABSTRACT Functional verification is critical in the development of today s complex digital

More information

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS Embedded System System Set of components needed to perform a function Hardware + software +. Embedded Main function not computing Usually not autonomous

More information

Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces

Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces Li Chen, Staff AE Cadence China Agenda Performance Challenges Current Approaches Traffic Profiles Intro Traffic Profiles Implementation

More information

NoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions

NoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions NoC Generic Scoreboard VIP by François Cerisier and Mathieu Maisonneuve, Test and Verification Solutions Abstract The increase of SoC complexity with more cores, IPs and other subsystems has led SoC architects

More information

Implementing debug. and trace access. through functional I/O. Alvin Yang Staff FAE. Arm Tech Symposia Arm Limited

Implementing debug. and trace access. through functional I/O. Alvin Yang Staff FAE. Arm Tech Symposia Arm Limited Implementing debug and trace access through functional I/O Alvin Yang Staff FAE Arm Tech Symposia 2017 Agenda Debug and trace access limitations A new approach Protocol based Bare metal vs mission mode

More information

Optimizing Hardware/Software Development for Arm-Based Embedded Designs

Optimizing Hardware/Software Development for Arm-Based Embedded Designs Optimizing Hardware/Software Development for Arm-Based Embedded Designs David Zhang / Cadence Zheng Zhang / Arm Agenda Application challenges in ML/AI and 5G Engines for system development and verification

More information

IMPLEMENTATION OF LOW POWER INTERFACE FOR VERIFICATION IP (VIP) OF AXI4 PROTOCOL

IMPLEMENTATION OF LOW POWER INTERFACE FOR VERIFICATION IP (VIP) OF AXI4 PROTOCOL e-issn 2455 1392 Volume 2 Issue 8, August 2016 pp. 1 8 Scientific Journal Impact Factor : 3.468 http://www.ijcter.com IMPLEMENTATION OF LOW POWER INTERFACE FOR VERIFICATION IP (VIP) OF AXI4 PROTOCOL Bhavana

More information

TRACE32. Product Overview

TRACE32. Product Overview TRACE32 Product Overview Preprocessor Product Portfolio Lauterbach is the world s leading manufacturer of complete, modular microprocessor development tools with 35 years experience in the field of embedded

More information

Attack Your SoC Power Challenges with Virtual Prototyping

Attack Your SoC Power Challenges with Virtual Prototyping Attack Your SoC Power Challenges with Virtual Prototyping Stefan Thiel Gunnar Braun Accellera Systems Initiative 1 Agenda Part #1: Power-aware Architecture Definition Part #2: Power-aware Software Development

More information

Co-Design and Co-Verification using a Synchronous Language. Satnam Singh Xilinx Research Labs

Co-Design and Co-Verification using a Synchronous Language. Satnam Singh Xilinx Research Labs Co-Design and Co-Verification using a Synchronous Language Satnam Singh Xilinx Research Labs Virtex-II PRO Device Array Size Logic Gates PPCs GBIOs BRAMs 2VP2 16 x 22 38K 0 4 12 2VP4 40 x 22 81K 1 4

More information

It's not about the core, it s about the system

It's not about the core, it s about the system It's not about the core, it s about the system Gajinder Panesar, CTO, UltraSoC gajinder.panesar@ultrasoc.com RISC-V Workshop 18 19 July 2018 Chennai, India Overview Architecture overview Example Scenarios

More information

Extending the Power of FPGAs

Extending the Power of FPGAs Extending the Power of FPGAs The Journey has Begun Salil Raje Xilinx Corporate Vice President Software and IP Products Development Agenda The Evolution of FPGAs and FPGA Programming IP-Centric Design with

More information

Combining TLM & RTL Techniques:

Combining TLM & RTL Techniques: Combining TLM & RTL Techniques: A Silver Bullet for Pre-Silicon HW/SW Integration Frank Schirrmeister EDPS Monterey April 17 th 2014 Hardware/Software Systems Software Bare Metal Applications Communications

More information

FPGA Adaptive Software Debug and Performance Analysis

FPGA Adaptive Software Debug and Performance Analysis white paper Intel Adaptive Software Debug and Performance Analysis Authors Javier Orensanz Director of Product Management, System Design Division ARM Stefano Zammattio Product Manager Intel Corporation

More information

Building blocks for 64-bit Systems Development of System IP in ARM

Building blocks for 64-bit Systems Development of System IP in ARM Building blocks for 64-bit Systems Development of System IP in ARM Research seminar @ University of York January 2015 Stuart Kenny stuart.kenny@arm.com 1 2 64-bit Mobile Devices The Mobile Consumer Expects

More information

Lorenz Kolb, Missing Link Electronics

Lorenz Kolb, Missing Link Electronics Lorenz Kolb, Missing Link Electronics Testkonzepte für FPGA/ASIC-Entwicklung nach 50 Jahren Moore s Law We are a Silicon Valley based technology company with offices in Germany. We are partner of leading

More information

Using Mentor Questa for Pre-silicon Validation of IEEE based Silicon Instruments by CJ Clark & Craig Stephan, Intellitech Corporation

Using Mentor Questa for Pre-silicon Validation of IEEE based Silicon Instruments by CJ Clark & Craig Stephan, Intellitech Corporation Using Mentor Questa for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments by CJ Clark & Craig Stephan, Intellitech Corporation INTRODUCTION IEEE 1149.1-2013 is not your father s JTAG.

More information

esi-risc Development Suite Getting Started Guide

esi-risc Development Suite Getting Started Guide 1 Contents 1 Contents 2 2 Overview 3 3 Starting the Integrated Development Environment 4 4 Hello World Tutorial 5 5 Next Steps 8 6 Support 10 Version 2.5 2 of 10 2011 EnSilica Ltd, All Rights Reserved

More information

Copyright 2016 Xilinx

Copyright 2016 Xilinx Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building

More information

Designing a Multi-Processor based system with FPGAs

Designing a Multi-Processor based system with FPGAs Designing a Multi-Processor based system with FPGAs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer / Consultant Cereslaan

More information

Software Verification for Low Power, Safety Critical Systems

Software Verification for Low Power, Safety Critical Systems Software Verification for Low Power, Safety Critical Systems 29 Nov 2016, Simon Davidmann info@imperas.com, Imperas Software Ltd. Page 1 Software Verification for Low Power, Safety Critical Systems Page

More information

OCP Engineering Workshop - Telco

OCP Engineering Workshop - Telco OCP Engineering Workshop - Telco Low Latency Mobile Edge Computing Trevor Hiatt Product Management, IDT IDT Company Overview Founded 1980 Workforce Approximately 1,800 employees Headquarters San Jose,

More information

Using Virtual Platforms To Improve Software Verification and Validation Efficiency

Using Virtual Platforms To Improve Software Verification and Validation Efficiency Using Virtual Platforms To Improve Software Verification and Validation Efficiency Odin Shen Staff FAE Arm Arm Tech Symposia Taiwan 2017 Software complexity and best practices Software Costs Increasing

More information

Efficient Failure Triage with Automated Debug: a Case Study by Sean Safarpour, Evean Qin, and Mustafa Abbas, Vennsa Technologies Inc.

Efficient Failure Triage with Automated Debug: a Case Study by Sean Safarpour, Evean Qin, and Mustafa Abbas, Vennsa Technologies Inc. Efficient Failure Triage with Automated Debug: a Case Study by Sean Safarpour, Evean Qin, and Mustafa Abbas, Vennsa Technologies Inc. Functional debug is a dreadful yet necessary part of today s verification

More information

S2C K7 Prodigy Logic Module Series

S2C K7 Prodigy Logic Module Series S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device

More information

Hardware/Software Co-Verification Using the SystemVerilog DPI

Hardware/Software Co-Verification Using the SystemVerilog DPI Hardware/Software Co-Verification Using the SystemVerilog DPI Arthur Freitas Hyperstone GmbH Konstanz, Germany afreitas@hyperstone.com Abstract During the design and verification of the Hyperstone S5 flash

More information

The protocol can efficiently use interconnect and fabric techno-

The protocol can efficiently use interconnect and fabric techno- Key Features Decodes NVMe Traffic CATC View Spreadsheet View 3 Window View Detail View TCG Decodes Queue and Device Tracking Long Trace Recording Low Power State Support Auto NVMe PCIe SSD Base Register

More information

Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)

Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation) Pranav Kumar, Staff Engineer Digvijaya Pratap SINGH, Sr. Staff Engineer STMicroelectronics, Greater NOIDA,

More information

Simulation Based Analysis and Debug of Heterogeneous Platforms

Simulation Based Analysis and Debug of Heterogeneous Platforms Simulation Based Analysis and Debug of Heterogeneous Platforms Design Automation Conference, Session 60 4 June 2014 Simon Davidmann, Imperas Page 1 Agenda Programming on heterogeneous platforms Hardware-based

More information

Silicon Penguins: Using and verifying an open source processor in a 100% first time right commercial ASIC

Silicon Penguins: Using and verifying an open source processor in a 100% first time right commercial ASIC Silicon Penguins: Using and verifying an open source processor in a 100% first time right commercial ASIC Declan Staunton System IC Business Unit Silicon & Software Systems Dublin, Ireland declan.staunton@s3group.com

More information

ELCT 912: Advanced Embedded Systems

ELCT 912: Advanced Embedded Systems ELCT 912: Advanced Embedded Systems Lecture 2-3: Embedded System Hardware Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering Embedded System Hardware Used for processing of

More information

Lesson 6 Intel Galileo and Edison Prototype Development Platforms. Chapter-8 L06: "Internet of Things ", Raj Kamal, Publs.: McGraw-Hill Education

Lesson 6 Intel Galileo and Edison Prototype Development Platforms. Chapter-8 L06: Internet of Things , Raj Kamal, Publs.: McGraw-Hill Education Lesson 6 Intel Galileo and Edison Prototype Development Platforms 1 Intel Galileo Gen 2 Boards Based on the Intel Pentium architecture Includes features of single threaded, single core and 400 MHz constant

More information

Embedded Hardware and Software

Embedded Hardware and Software Embedded Hardware and Software Saved by a Common Language? Nithya A. Ruff, Director, Product Marketing 10/11/2012, Toronto Synopsys 2012 1 Synopsys Industry Leadership $1,800 $1,600 $1,400 $1,200 $1,000

More information

WS_CCESSH5-OUT-v1.01.doc Page 1 of 7

WS_CCESSH5-OUT-v1.01.doc Page 1 of 7 Course Name: Course Code: Course Description: System Development with CrossCore Embedded Studio (CCES) and the ADI ADSP- SC5xx/215xx SHARC Processor Family WS_CCESSH5 This is a practical and interactive

More information

Module Introduction. CONTENT: - 8 pages - 1 question. LEARNING TIME: - 15 minutes

Module Introduction. CONTENT: - 8 pages - 1 question. LEARNING TIME: - 15 minutes Module Introduction PURPOSE: The intent of this module is to introduce a series of modules that explain important features of Motorola s i.mx applications processors. OBJECTIVES: - Explain the need for

More information