90-nm To 10-nm Physical IP For Wearable Devices & Application Processors Navraj Nandra Synopsys, Inc. All rights reserved. 1

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1 90-nm To 10-nm Physical IP For Wearable Devices & Application Processors Navraj Nandra 2015 Synopsys, Inc. All rights reserved. 1

2 Process Requirements are Specific to Customer/Market Need Wearable / IoT has given impetus to established nodes Application processors drive FinFET roadmap to 10-nm 2015 Synopsys, Inc. All rights reserved. 2

3 Market Requirements for Wearables Driving Physical IP Specifications Low-end wearable 90-nm moving to 55-nm Embedded flash 4-7 metal layers USB 2.0, ADC, standard cells, memory High-end wearable Moving to 28-nm MIPI CSI, DSI, LPDDR3/2, ADC ~8 metal layers UART GPIO USB Host OTG w/ Charge Detect Radio (Bluetooth Smart / ) System Logic Sensor Subsystem ARC EM Processor I2C SPI Internal Flash SRAM / ROM ADC / Comparator Low-end wearable DAC / PWM / Timers 2015 Synopsys, Inc. All rights reserved. 3

4 Processor Processor Market Req s for Application Processors Driving Physical IP Specifications Today s application processors GPIO LPDDR Flash SD emmc UFS SATA 28-nm moving to 16/14FF 1.8 V; >8 metal layers USB 3.0, SERDES, MIPI, HDMI, LPDDR, ADC, high-performance standard cells & memory Next-gen application processor Moving to 10-nm UART I2C 3G/4G Modem WiFi Link De-Bug Clock Battery Trace L3 Cache L2 Cache Keypad Processor Processor 3D Graphics Video Accelerator Image Sensor Processor Security Processor I2C/SPI Touchscreen Audio Processor HDMI 2.0 USB SS/ HS Host/ Device Audio Analog FE Headset, Speaker, Amplifier MIPI CSI MIPI DSI USB 3.1, Type-C connector, next-gen SERDES, HDMI & MIPI protocols Application Processor 2015 Synopsys, Inc. All rights reserved. 4

5 USB IP Technical Requirements Key Parameters USB 2.0 for Wearables 90- to 55-nm USB 3.1 for Application Processors 16/14FF, 10FF Power < 100 mw (480Mbit/s) < 100 mw (5 Gbit/s) < 100 mw (10 Gbit/s) Area Small Tiny I/O 2.5 V / 3.3 V (1.8 V 28-nm) 1.8V (1.5V, 1.2V) Metal stack 6 layers 9-10 layers ESD 2kV HBM, 500V CDM 2kV HBM, 250V CDM USB charging YES, device only YES, host and device 2015 Synopsys, Inc. All rights reserved. 5

6 USB Type-C Connector One symmetrical cable, inserted either way 24 pins: power, HS, SS, config, sideband Passive adapters for existing type-a and type-b No direction - same connector for host/hub, device Data, charging, analog audio in one connector Small, robust, EMI/RFI improved, expandable USB 3.1 Type C USB 3.1 Standard A 2015 Synopsys, Inc. All rights reserved. 6 USB 3.1 Micro-B Confidential

7 SERDES Technical Requirements Key Parameters Wearables 90- to 55-nm Application Processors 16/14FF, 10FF Bandwidth Up to 5 Gbps Up to 8 Gbps Active Power mw s ~mw s Stand-by power mw s mw s Area Small Tiny Beach front Not critical Critical I/O Voltage 2.5V or 3.3V 1.8V 1.5V 1.2V Metal stack 6 layers 8-10 layers +RDL ESD 2kV HBM, 500V CDM 2kV HBM, 250V CDM Package type Wirebond, Flip chip Flip chip BOM Cost Single Vt, 6LM, WB Multi-Vt, 8 to 10LM, FC Features Low quality REFCLK, L1S, power gating Refclk buffer, L1S, power gating 2015 Synopsys, Inc. All rights reserved. 7

8 SERDES Comparison 90-nm / 55-nm Versus 16FF 90-nm 65-nm 16-nm Reduced area, beach front, power Improved performance with added features 2015 Synopsys, Inc. All rights reserved. 8

9 DDR IP Technical Requirements Key Parameters Wearables 90- to 55-nm Protocols LPDDR2/3 LPDDR3/4 Application Processors 16/14FF, 10FF Data Rates Mbps Up to 3200 Mbps Power Dependent on speed power lower Area small larger Dependent on speed power higher I/O Voltage 2.5V 1.8V 1.5V Metal stack 6 layers 8-10 layers + RDL ESD 2kV HBM, 500V CDM 2kV HBM, 250V CDM Termination Required No Yes Package type Wirebond Flip chip Features Simple training More complex training, per bit deskew 2015 Synopsys, Inc. All rights reserved. 9

10 DDR Evolves with the Protocols 90-nm / 55-nm Versus 16/14FF 90-nm / 55-nm LPDDR2/3 PHY, up to 1066 Mbps, DLL based PHY, added simpler IO, limited training 16/14-nm LPDDR4/3 PHY, up to 3200 Mbps, PLL based PHY, complex IO w/pre-emphasis, complex training plus Vref generation & per bit deskew 2015 Synopsys, Inc. All rights reserved. 10

11 Logic Library Technical Requirements Advanced Power Management: 90/55nm IoT & 16/14FF APs Key Parameters Power Track Height Wearables 90- to 55-nm Both thin and thick oxide libraries include multi-bit flops, Power Optimization Kit for DVFS and shutdown Thin Oxide 6/7 track for ultra high density logic Thick Oxide - 10 track for wake-up logic Application Processors 16/14FF Power Kit for DVFS and shutdown, highest speeds require robust design for IR/EM challenges, MBFFs 10.5 for fastest processors, 9 track for GPU & mid. CPU, 7.5 track for slower parts of SOC Performance 10MHz 50MHz 500MHz 3GHz Metal stack Challenges Cells only use up to M2 but support routing stacks from 5 to 7 Support routing up to 12 layers with RDL Low voltage characterization Power and signal EM 2015 Synopsys, Inc. All rights reserved. 11

12 Logic Library Power Management Innovative Circuits Integrated into Design Flows with UPF Power D1 Master latch Slave latch Q1 Clk Clk VDDI VDDO IN LS OUT Clk VSS Level Shifter D2 Master latch Slave latch Q Synopsys, Inc. All rights reserved. 12

13 Thick Oxide Library Lowest leakage for always-on wakeup circuits Thick oxide for gates Filler cells for routing UART GPIO USB Host OTG w/ Charge Detect Radio (Bluetooth Smart / ) System Logic Sensor Subsystem ARC EM Processor I2C SPI Internal Flash SRAM / ROM ADC / Comparator DAC / PWM / Timers Color indicates typical Keep Alive circuits 2015 Synopsys, Inc. All rights reserved. 13

14 Memory IP Technical Requirements Different Applications Have Different Requirements Key Parameters Wearable 90- to 55-nm CMOS Image Sensor 90- to 40-nm Application processor 16/14FF Performance 10 MHz 50 MHz 100 MHz 200 MHz 500 MHz 3 GHz Area As small as possible As small as possible 500 MHz domains need to be as small as possible Power Requires ultra low voltage operation and low leakage state retention; May require assist circuitry to support low voltage operation Requires low power memories Requires low leakage memories Metal Stack Support M6 top level metal Support M4 top level metal Support M10 top level metal Memories required High Density & Low Power Memory (Single Port, Two Port and ROM) High Density & Low Power Memory (Single Port, Two Port and ROM) High Speed (Single Port) High Density & Low Power (Single Port, Two Port, Dual Port and ROM); Customized memory for CPU, GPU and DSP cores 2015 Synopsys, Inc. All rights reserved. 14

15 Low Power SRAMs and ROMs Ideal for IoT Devices SRAM Retention Mode Ultra low power ROM Shutdown mode for maximum leakage reduction Source biasing to reduce leakage by 70% while retaining data Ultra low voltage operation ROM Shut Down Mode Single Signal Power Down Bringing advanced power management design techniques to mature nodes Zero-Array ROM for further power reduction Shutdown mode with integrated power gates Easy User Interface, Controlled by a Single Pin 2015 Synopsys, Inc. All rights reserved. 15

16 Integrated Test & Repair with Synopsys Memories SRAM - LT SRAM - IT SRAM - ST Row Decoders Control Memory Array Sense Amp and Output buffers Row Decoders Control Memory Array Sense Amp and Output buffers Integrated Test (partial SMS IP) Row Decoders Control Memory Array Sense Amp and O/P buffers Integrated Test (partial SMS IP) R e d u n d a n c y Control Signals Input /Output Data Control Signals Input /Output Data Control Signals Input /Output Data STAR Memory System STAR Memory System STAR Memory System Input/Output Data, Control Signals Input/Output Data, Control Signals Input/Output Data, Control Signals efuse Faster Design Closure Reduced Area Higher Performance Higher ATPG Coverage 2015 Synopsys, Inc. All rights reserved. 16

17 Continued Innovation in Memory IP Now Extending Expertise to 10-nm FinFET / / 55 45/ 40 32/ 28 22/ 20 16/ High- Density Compilers High- Speed Compilers Ultra LP w/array Biasing Router Friendly Library Self Test & Repair Memories for CMOS Image Sensor Metal Program Library Ultra High- Density 2P High- Speed Async. RF High Density Memory 55-nm 8M SP SRAM Light Sleep Deep Sleep For IOT Power Optimize Kit Lib Advanced Test Chip Architecture with High- Speed Test & Diagnostics Integrated Power Gating Periphery VT Dual Voltage Rails Long Channel Libs Unidirectional Poly Enhanced In-rush Current Mgmt HPC Kit & Datapath Library Read/ Write Assist Enhanced Reference Circuitry Ultra Low Voltage Operation Process Fast Monitors Retention Enhanced Bringing advanced Test power Long assist Channel circuitry Memory process FinFETs nodes / DPT Gate/VT Bias Libs Silicon Test Structures High Speed Memory 16/14-nm PODE/ CPODE FinFET Near Retention Voltage Operation Triple Pattern Router Support management back to mature Partnering with all FinFET foundries 14/16nm development started in nm development in mutliple foundries 2015 Synopsys, Inc. All rights reserved. 17

18 IEEE 1500 DesignWare STAR Memory System Test, Repair and Diagnostics of FinFET and Planar Memories 2013 Best-in-Test Test-of-Time Award Winner Cache Group 1 CPU Cache Group 2 Test Bus Test Bus MMB Processor MMB Processor Efuse SMS Server IEEE 1500 SoC TAP High test quality Faster design closure High yield & reliability Advanced diagnostics SMS Processor IEEE 1500 SMS Processor Wrapper Wrapper Wrapper Wrapper 2P RF 1P RF DP SRAM EXTRAM 2015 Synopsys, Inc. All rights reserved. 18

19 Industry s First On-Chip Memory Test & Repair Solution for Embedded Flash DesignWare STAR Memory System for Embedded Flash Cuts Test Cost by 20% Provides comprehensive test coverage & in-field diagnostics of embedded flash memories Eliminates the need for expensive external test solutions for embedded flash memories Reduces overall design integration effort, development cycle and test cost 2015 Synopsys, Inc. All rights reserved. 19

20 ADC IP Technical Requirements Key Parameters Power Area Wearable / MCU 90- to 55-nm 10 s to 100 s low speed 10 s power down 0.15 mm mm 2 for additional features Application & Baseband Processor 28-nm to 16FF 1 s to 10 s high speed 0.04 mm 2 for large MIMO I/O 3.3 V supply compatible 1.8 V supply compatible Metal Stack 5 layers 7 layers Process Options Standard logic, eflash compatible Standard logic Internal Calibration Yes Yes Power Saving Modes Automatic power scaling with speed Power down modes Internal power switch / LDO Automatic power scaling with speed Power down modes Fast wake-up cycles Max Sampling rate Up to 5MSPS Up to 320MSPS GSPS Resolution 12-bit -> 16-bit 12-bit Additional Features Use Case Analog input multiplexer (rail-to-rail, single ended and differential) Wide supply range (3.6V <> 1.62V) Sensor / General purpose data acquisition No external reference circuitry Companion TX-DAC & PLL for AFE Baseband wireless / wireline AFE Digital TV 2015 Synopsys, Inc. All rights reserved. 20

21 Analog IP for IoT ADC s for MCUs & the Sensor Interface Broad portfolio of silicon-proven IP Compatible with embedded flash Higher performance than general purpose MCU ADCs on the market Low current consumption Long idle times Ultra-low leakage Flexibility of use High linearity, low offset, for absolute accuracy 2015 Synopsys, Inc. All rights reserved. 21

22 Analog IP for Application Processor Data Converters for easy integration in Advanced SoCs Complete High Performance portfolio 12-bit 80/160/320 MSPS ADC 12-bit 640 MSPS DAC 12-bit 5 MSPS Aux ADC & DAC Video DAC & Analog Audio Codec Companion low jitter PLL Ideal for multiple applications Wireless/Mobile: LTE-A, WiFi ac Digital TV/Multimedia Wired communications Featuring Most compact and low power Internal digital calibration for robustness Low BOM and pin count IP Innovation for 28-nm and Beyond Lowest power and compact area SAR-based 12-bit ADC ADC Product Area (mm 2 ) Power (mw) 12-b 80 MSPS b 160 MSPS b 320 MSPS Synopsys, Inc. All rights reserved. 22

23 12-bit 80MSPS ADC Evolution Keeping up w/ Moore s Law with State of the Art Architectures 45 x area improvement 120 x power reduction Standard logic processes 180nm 1.8 mm mw 65nm 0.34 mm mw 28nm 0.04 mm mw 2015 Synopsys, Inc. All rights reserved. 23

24 Summary Wearable / IoT has given impetus to established nodes Application processors drive FinFET roadmap to 10-nm Design approaches and semiconductor requirements for physical IP are driven by divergent market needs To be successful in both markets, IP vendors must tailor the IP to the specific requirements Significant application know-how Experience with multiple process technologies 2015 Synopsys, Inc. All rights reserved. 24

25 2015 Synopsys, Inc. All rights reserved. 25 Thank You