Real-Timeness and System Integrity on a Asymmetric Multi Processing configuration
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1 Real-Timeness and System Integrity on a Asymmetric Multi Processing configuration D&E Event November 2nd Relator: Manuele Papais Sales & Marketing Manager 1
2 DAVE Embedded Systems DAVE Embedded Systems' HEADQUARTER Via Talponedo, 29/A Porcia, Italy DAVE Embedded Systems' BRANCH OFFICE Maximilianstrasse, München, Germany
3 DAVE Embedded Systems Sales Offices: USA California UK Swindon France Paris Israel Tel Aviv Belgium / The Netherlands Telerex B.V. Now opening: Japan DAVE Embedded Systems' HEADQUARTER Via Talponedo, 29/A Porcia, Italy DAVE Embedded Systems' BRANCH OFFICE Maximilianstrasse, München, Germany
4 DAVE Embedded Systems Concept and Design of Embedded Systems
5 DAVE Embedded Systems Solutions Provider Concept and Design of Embedded Systems Supporting and Promoting Customer Ideas and Concepts from Scratch to Business
6 Products Portfolio
7 Products Portfolio System On Modules Texas Instruments SITARA, DA VINCI NXP i.mx6... XILINX Zynq
8 Products Portfolio System On Modules Single Board Computers Texas Instruments SITARA, DA VINCI Wall mount NXP i.mx6... DIN Bar mount XILINX Zynq
9 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq
10 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq Available with advanced SW elements
11 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq Available with advanced SW elements Linux Kernel & Drivers
12 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq Available with advanced SW elements Linux Kernel & Drivers Android BSP
13 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq Available with advanced SW elements Linux Kernel & Drivers Android BSP FPGA Vivado Project and SDSoC/HLS examples
14 Products Portfolio System On Modules Single Board Computers Customized Solutions Texas Instruments SITARA, DA VINCI Wall mount Based on customer requirements NXP i.mx6... DIN Bar mount Based on existing proven solutions XILINX Zynq Available with advanced SW elements Linux Kernel & Drivers Android BSP FPGA Vivado Project and SDSoC/HLS examples RTOS Integration/examples
15 AMP Asymmetric Multi Processing BIG - LITTLE NXP Vybrid TI AM335...
16 AMP Asymmetric Multi Processing BIG - LITTLE SIMMETRIC NXP Vybrid TI AM NXP i.mx6 DUAL Lite NXP i.mx6 DUAL NXP i.mx6 QUAD...
17 AMP Asymmetric Multi Processing BIG - LITTLE SIMMETRIC NXP Vybrid TI AM NXP i.mx6 DUAL Lite NXP i.mx6 DUAL NXP i.mx6 QUAD...
18 Cortex-A9 architecture Multicore platform approach Low power architecture Industrial grade proof
19 Cortex-A9 architecture Multicore platform approach Low power architecture Industrial grade proof TrustZone IP integrated
20 Cortex-A9 architecture Multicore platform approach Low power architecture Industrial grade proof TrustZone IP integrated NXP i.mx6
21 Cortex-A9 architecture Multicore platform approach Low power architecture Industrial grade proof TrustZone IP integrated NXP i.mx6 Xilinx Zynq
22 Cortex-A9 architecture Multicore platform approach Low power architecture Industrial grade proof TrustZone IP integrated NXP i.mx6 Xilinx Zynq
23 The TrustZone IP Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone
24 The Asymmetric Multi Processing on Zynq Architecture AXI bus Processing System (PS) Programmable Logic (PL) FPGA
25 The Asymmetric Multi Processing on Zynq Architecture AXI bus Processing System (PS) Programmable Logic (PL) FPGA Hard Real Time
26 The Asymmetric Multi Processing on Zynq Architecture RTOS / Bare Metal Real Time AXI bus Processing System (PS) Programmable Logic (PL) FPGA Hard Real Time
27 The Asymmetric Multi Processing on Zynq Architecture Linux No - Real Time RTOS / Bare Metal Real Time AXI bus Processing System (PS) Programmable Logic (PL) FPGA Hard Real Time
28 The Asymmetric Multi Processing on Zynq Architecture Processing System (PS) AXI bus ASYNC Comm Programmable Logic (PL) FPGA SHARED Data Linux No - Real Time RTOS / Bare Metal Real Time Hard Real Time
29 The Asymmetric Multi Processing on Zynq Architecture Processing System (PS) AXI bus INTEGRITY ASYNC Comm Programmable Logic (PL) FPGA SHARED Data Linux No - Real Time RTOS / Bare Metal Real Time Hard Real Time
30 The Asymmetric Multi Processing on Zynq Architecture Processing System (PS) 1st boot Master AXI bus ASYNC Comm INTEGRITY 2nd Slave Programmable Logic (PL) FPGA SHARED Data Linux No - Real Time RTOS / Bare Metal Real Time Hard Real Time
31 The Asymmetric Multi Processing on Zynq Architecture Processing System (PS) L2 Cache 1st boot Master AXI bus ASYNC Comm INTEGRITY 2nd Slave Programmable Logic (PL) FPGA SHARED Data Linux No - Real Time RTOS / Bare Metal Real Time Hard Real Time
32 The Asymmetric Multi Processing on Zynq Architecture Processing System (PS) L2 Cache 1st boot Master AXI bus ASYNC Comm INTEGRITY 2nd Slave Programmable Logic (PL) FPGA SHARED Data Linux No - Real Time RTOS / Bare Metal Real Time Hard Real Time Traditional AMP has not ALL these feature so, integrate all new feature listed?
33 The TrustZone-based Approach Processing System (PS) AXI bus Programmable Logic (PL) FPGA It is required a Software Monitor
34 The TrustZone-based Approach SAFEG monitor with TrustZone AXI bus Processing System (PS) Programmable Logic (PL) FPGA It is required a Software Monitor Customized version of SAFEG
35 The TrustZone-based Approach SAFEG monitor with TrustZone TRUST No TRUST OS (RTOS) OS (GPOS) SAFEG monitor with TrustZone AXI bus Processing System (PS) Programmable Logic (PL) FPGA It is required a Software Monitor Customized version of SAFEG The monitor is responsible for: Enable TrustZone IP Initialize Trusted /Non Trusted areas
36 The TrustZone - based Approach Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone
37 The TrustZone - based Approach SPI UART1 Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone UART2 NS SS NS
38 The TrustZone - based Approach SPI UART1 Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone UART2 NS SS NS
39 The TrustZone - based Approach CORE0 CORE1 S SPI S NS UART1 Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone UART2 NS SS NS
40 The TrustZone - based Approach CORE0 CORE1 S SPI S NS UART1 Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone UART2 NS SS NS
41 The TrustZone - based Approach X Not allowed CORE0 CORE1 S SPI S NS UART1 Like the 33rd bit Transaction (S)ecure / (NS)Non Secure) Trustzone UART2 NS SS NS
42 The TrustZone - based Approach X Not allowed CORE0 CORE1 S SPI S NS UART1 Like the 33rd bit UART2 NS SS NS Transaction (S)ecure / (NS)Non Secure) This applies to: Cores DMA... Trustzone For INTC... Linux must ask to Monitor The OK for modify INTC
43 The TrustZone-based Approach AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone TRUST No TRUST OS (RTOS) OS (GPOS) SAFEG monitor with TrustZone DATA I/O RTOS DATA BUS GPOS DATA It is required a Software Monitor Customized version of SAFEG The monitor is responsible for: Enable TrustZone IP Initialize Trusted /Non Trusted areas Setup data struct and except handlers Memory RTOS GPOS Memory Memory
44 The TrustZone-based Approach AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone MASTER SLAVE TRUST No TRUST OS (RTOS) OS (GPOS) SAFEG monitor with TrustZone DATA I/O RTOS DATA BUS GPOS DATA It is required a Software Monitor Customized version of SAFEG The monitor is responsible for: Enable TrustZone IP Initialize Trusted /Non Trusted areas Setup data struct and except handlers Start Trusted OS Memory RTOS GPOS Memory Memory
45 DAVE Embedded Systems' example SAFEG monitor with TrustZone AXI bus Processing System (PS) Programmable Logic (PL) FPGA
46 DAVE Embedded Systems' example SAFEG monitor with TrustZone Statically assigned OS AXI bus Processing System (PS) Programmable Logic (PL) FPGA
47 DAVE Embedded Systems' example SAFEG monitor with TrustZone Statically assigned OS 100% No Trusted Linux AXI bus Processing System (PS) Programmable Logic (PL) FPGA
48 DAVE Embedded Systems' example SAFEG monitor with TrustZone Statically assigned OS 100% No Trusted Linux 100% Trusted FreeRTOS No context switch Reduced latency AXI bus Processing System (PS) Programmable Logic (PL) FPGA
49 DAVE Embedded Systems' example AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone Statically assigned OS Statically partinioned Mem partitioning 100% No Trusted Linux 100% Trusted FreeRTOS No context switch Reduced latency
50 DAVE Embedded Systems' example AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone Statically assigned OS Statically partinioned Mem partitioning 100% No Trusted Linux 100% Trusted FreeRTOS No context switch Reduced latency No trusted private Area (MMU level)
51 DAVE Embedded Systems' example AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone Statically assigned OS Statically partinioned Mem partitioning 100% No Trusted Linux 100% Trusted FreeRTOS No trusted private Area (MMU level) No context switch Reduced latency Trusted private Area (TrustZone level)
52 DAVE Embedded Systems' example AXI bus Processing System (PS) Programmable Logic (PL) FPGA SAFEG monitor with TrustZone Statically assigned OS Statically partinioned Mem partitioning 100% No Trusted Linux 100% Trusted FreeRTOS No trusted private Area (MMU level) No context switch Reduced latency Trusted private Area (TrustZone level) Shared Area (Not Trusted)
53 Details: The MEM partinioning Mem partitioning END of SDRAM LINUX 0x RPMSG buffer and shared data 0x Monitor 0x FreeRTOS 0x
54 Details: The BOOT process 0 RESET
55 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory
56 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory 2 FSBL: SDRAM init and Uboot image load in memory
57 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory 2 FSBL: SDRAM init and Uboot image load in memory 3 Uboot: loads in SDRAM: Monitor Trusted code FREERTOS No Trusted code LINUX
58 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory 2 FSBL: SDRAM init and Uboot image load in memory 3 Uboot: loads in SDRAM: Monitor Trusted code FREERTOS No Trusted code LINUX 4 Uboot: gives control to Monitor
59 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory 2 FSBL: SDRAM init and Uboot image load in memory 3 Uboot: loads in SDRAM: Monitor Trusted code FREERTOS No Trusted code LINUX 4 Uboot: gives control to Monitor 5 Monitor: Init TrustZone Enable data structures and Handlers for both cores Gives to Trust code the control of machine FREERTOS MASTER
60 Details: The BOOT process 0 RESET 1 BootROM: FSBL taken from NV-memory and loaded on On Chip Memory 2 FSBL: SDRAM init and Uboot image load in memory 3 Uboot: loads in SDRAM: Monitor Trusted code FREERTOS No Trusted code LINUX 4 Uboot: gives control to Monitor 5 Monitor: Init TrustZone Enable data structures and Handlers for both cores Gives to Trust code the control of machine FREERTOS 6 RTOS FreeRTOS: Under his control decides to start No Trusted OS (LINUX) MASTER SLAVE
61 Details: Inter-World comm Several methods available OP - TEE dualoscom Based on TOPPERS Very specific Too SW layers RPMsg Based on TI DSP accepted on mainline Used by Xilinx in AN Very well structured on buffers and cache handlings OpenAMP Similar to RPMsg Used on MPSoCs
62 Details: Inter-World comm Several methods available OP - TEE dualoscom RPMsg Selection Criterias OpenAMP
63 Details: The BOOT process Several methods available OP - TEE dualoscom RPMsg Selection Criterias Acceptance into Mainline Linux Kernel OpenAMP
64 Details: The BOOT process Several methods available OP - TEE dualoscom RPMsg OpenAMP Selection Criterias Acceptance into Mainline Linux Kernel Control over the isolation level between the two worlds
65 Details: The BOOT process Several methods available OP - TEE dualoscom RPMsg OpenAMP Selection Criterias Acceptance into Mainline Linux Kernel Maintenance future developments Control over the isolation level between the two worlds
66 Details: The BOOT process Several methods available OP - TEE dualoscom RPMsg OpenAMP Selection Criterias Acceptance into Mainline Linux Kernel Maintenance future developments Control over the isolation level between the two worlds The level of isolation is application dependent
67 Details: The BOOT process Several methods available OP - TEE dualoscom RPMsg OpenAMP Selection Criterias Acceptance into Mainline Linux Kernel Maintenance future developments Control over the isolation level between the two worlds The level of isolation is application dependent
68 Details: L2 cache management Processing System (PS) FreeRTOS Trusted AXI bus LINUX No Trusted Programmable Logic (PL) FPGA
69 Details: L2 cache management LINUX No Trusted FreeRTOS Trusted L1 cache L1 cache MMU MMU AXI bus Processing System (PS) Programmable Logic (PL) FPGA
70 Details: L2 cache management LINUX No Trusted FreeRTOS Trusted L1 cache L1 cache MMU MMU SHARED MEMORY AXI bus Processing System (PS) Programmable Logic (PL) FPGA PRIVATE MEMORY
71 Details: L2 cache management LINUX No Trusted FreeRTOS Trusted L1 cache L1 cache MMU MMU AXI bus Processing System (PS) Programmable Logic (PL) FPGA L2 cache PRIVATE MEMORY SHARED MEMORY PRIVATE MEMORY
72 Details: L2 cache management LINUX No Trusted FreeRTOS Trusted L1 cache L1 cache MMU MMU AXI bus Processing System (PS) Programmable Logic (PL) FPGA L2 cache PRIVATE MEMORY SHARED MEMORY PRIVATE MEMORY Linux performances are not affected by dual OS solutions FreeRTOS determinism is granted Shared mem is not cached
73 Details: L2 cache management LINUX No Trusted FreeRTOS Trusted L1 cache L1 cache MMU MMU OCM AXI bus Processing System (PS) Programmable Logic (PL) FPGA L2 cache PRIVATE MEMORY SHARED MEMORY PRIVATE MEMORY Linux performances are not affected by dual OS solutions FreeRTOS determinism is granted Shared mem is not cached Internal OCM can be granted only to Trust OS
74 Details: Performances achieved Processing System (PS) FreeRTOS Trusted AXI bus LINUX No Trusted Programmable Logic (PL) FPGA TEST BENCH: used the internal timer to measure the latency between: INT handling INT service
75 Details: Performances achieved Processing System (PS) IDLE Google Stress Test SAT FreeRTOS Trusted AXI bus LINUX No Trusted Programmable Logic (PL) FPGA
76 Details: Performances achieved LINUX No Trusted FreeRTOS Trusted IDLE IDLE Google Intensive Mem Stress Test SAT Task AXI bus Processing System (PS) Programmable Logic (PL) FPGA
77 Details: Performances achieved LINUX No Trusted FreeRTOS Trusted IDLE IDLE Latency Linux IDLE RTOS IDLE min 287ns avg 287ns max 548ns AXI bus Processing System (PS) Programmable Logic (PL) FPGA
78 Details: Performances achieved Processing System (PS) FreeRTOS Trusted IDLE Google Stress Test SAT Latency Linux IDLE RTOS IDLE LINUX SAT RTOS IDLE min 287ns 287ns avg 287ns 296ns max 548ns 539ns AXI bus LINUX No Trusted Programmable Logic (PL) FPGA
79 Details: Performances achieved Processing System (PS) FreeRTOS Trusted Google Intensive Mem Stress Test SAT Task AXI bus LINUX No Trusted Programmable Logic (PL) FPGA Latency Linux IDLE RTOS IDLE LINUX SAT RTOS IDLE LINUX SAT RTOS 16k task load min 287ns 287ns 287ns avg 287ns 296ns 205ns max 548ns 539ns 575ns Linux performances not affect RTOS in any condition FreeRTOS latency is granted with not heavy load tasks
80 Details: Performances achieved Processing System (PS) FreeRTOS Trusted Google Intensive Mem Stress Test SAT Task AXI bus LINUX No Trusted Programmable Logic (PL) FPGA Latency Linux IDLE RTOS IDLE LINUX SAT RTOS IDLE LINUX SAT RTOS 16k task load LINUX SAT RTOS 128k task load min 287ns 287ns 287ns 1268ns avg 287ns 296ns 205ns 2024ns max 548ns 539ns 575ns 3050ns Linux performances not affect RTOS in any condition FreeRTOS latency is granted with not heavy load tasks FreeRTos is affected by high mem loads due to it is not cached
81 Details: Performances achieved LINUX No Trusted FreeRTOS Trusted IDLE IDLE Google Intensive Mem Stress Test SAT Task AXI bus Processing System (PS) Programmable Logic (PL) FPGA Latency Linux IDLE RTOS IDLE LINUX SAT RTOS IDLE LINUX SAT RTOS 16k task load LINUX SAT RTOS 128k task load min 287ns 287ns 287ns 1268ns avg 287ns 296ns 205ns 2024ns max 548ns 539ns 575ns 3050ns Linux performances not affect RTOS in any condition FreeRTOS latency is granted with not heavy load tasks FreeRTos is affected by high mem loads due to it is not cached The L2 cache can be also used only on Trust OS there are pro and cons (typically a determinism reduction is noted)
82 Future works and references
83 Future works and references Complete Reboot of Slave core from Master Core
84 Future works and references Complete Reboot of Slave core from Master Core Deep understanding and optimization of INTerrupt handling and communication data interchange between two worlds related to determinism and latency aspects
85 Future works and references Complete Reboot of Slave core from Master Core Deep understanding and optimization of INTerrupt handling and communication data interchange between two worlds related to determinism and latency aspects Refers to: Yashu Gosain and Prushothaman Palanichamy, Xilinx WP429 - TrustZone Technology Support in Zynq-7000 All Programmable SoCs (v1.0), May 20, 2014 DAVE Embedded Systems, AN-BELK-001: Asymmetric Multiprocessing (AMP) on Bora Linux FreeRTOS, TOPPERS SafeG home page (English), -, and many others
86 Question and answers
87 DAVE S.r.l. Via Talponedo, 29/A I-33080, Porcia (PN) Italy Tel Fax wiki.dave.eu 87
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