Title: Using low-power dual-port for inter processor communication in next generation mobile handsets

Transcription

1 Title: Using low-power dual-port for inter processor communication in next generation mobile handsets Abstract: The convergence of mobile phones and other consumer-driven devices such as PDAs, MP3 players, digital still and video cameras is progressing rapidly as evidenced by recent introductions of phones like the Motorola ROKR and Palm Treo. Consequently, the demand for processing power is increasing exponentially in these high-performance, lowpower devices, and it becomes inevitable for mobile handset manufacturers to start adopting a dual processor architecture. In the case of a PDA or smart phone, the two processing elements are typically a baseband processor and an application processor. The two processors operate independently, performing specialized tasks in the mobile phone architecture. The baseband processor acts as an RF modem, while the application processor runs the operating system and handles other multimedia features. High level operating systems, such as Linux, Symbian and Windows CE/Mobile, usually require a powerful application processor that also manages the audio, video, and other wireless features such as Wi-Fi and Bluetooth. In 2G and 2.5G, the two processors are interconnected by a traditional serial interface, either UART or SPI. These serial standards provide a low-bandwidth solution typically not exceeding 1Mbps in throughput; just enough for low data rate traffic. However, with the proliferation of 3G/3.5G networks, the multimedia rich content boosts the inter-processor communication bandwidth requirement significantly. As a result, the use of conventional serial interfaces becomes insufficient in 3G/3.5G applications (real-time video, music, games, etc.). A new system-interconnect solution has recently emerged in the mobile handset space: the low-power dual-port memory. These dual-port memory devices are specifically designed for the wireless handset market to maximize throughput and minimize power consumption. The dual-ports have standard memory interfaces that can be connected seamlessly to all popular baseband and application processors. Moreover, by interfacing to the standard processor memory interface, the use of precious GPIO pins can also be minimized. To demonstrate the proof of concept, a platform using Texas Instruments (TI) OMAP1710 processors and a Cypress MoBL dual-port has been built and evaluated. This article highlights the effective throughput as measured from this demonstration platform, and outlines the value propositions of this high-performance, low-power dual-port interconnect solution against other Inter Processor Communication (IPC) alternatives.

2 Introduction The convergence of mobile phones and other consumer-driven devices such as PDAs, MP3 players, digital still and video cameras is progressing rapidly as evidenced by recent introductions of phones like the Motorola ROKR and Palm Treo. Consequently, a classic engineering paradox has arisen: an ultra high-performance portable hand-held device with extreme low-power consumption. Moreover, as the amount of processing power increases exponentially, it has become inevitable for mobile handset manufacturers and design houses to start adopting dual processor architectures. With the high data rates inherent in 3G/3.5G wireless systems, the bandwidth and latency of processor interconnects have skyrocketed in order to accommodate the requirements of multimedia features. In today s dual processor PDA and smart phone designs, the processing elements are typically a baseband processor and a function specific co-processor, such as an application or multimedia processor. The two processors operate independently, performing specialized tasks in the mobile handset. The baseband processor acts as an RF modem, while the application processor runs the operating system and handles various multimedia applications. Popular and complex operating systems, such as Linux, Symbian, and Windows CE/Mobile, require a powerful application processor that can also manage audio, video, and wireless features such as Wi-Fi and Bluetooth. Figure 1 below shows an example of such dual processor architecture in high-end mobile handsets. Figure 1: Dual Processor Architecture in 3G/3.5G Smart/PDA Handsets A data flow example is illustrated in the figure below. Voice and multimedia data is received on the antenna connected to the baseband processor and this data is then packetized and sent to the application processor. The application processor either stores the multimedia content in a file system or displays/plays it in real time. As we will see,

3 the interconnect bandwidth between the baseband and application processors can become a bottleneck in next generation 3G/3.5G wireless mobile handsets. Figure 2: Data Flow Example in Dual Processor Mobile Handsets Technology Bandwidth Requirement Even in high-end 2G and 2.5G wireless handset designs, dual processor architectures are widely implemented. However, the data rate in these networks is usually in the range of hundreds of kilobits per second, as most of the traffic is voice and simple s and text messages. Therefore, the inter-processor communication (IPC) in the current generation of wireless handsets is usually handled by serial interfaces like SPI, UART, or USB which need to be available on both processors. For instance, the GPRS and EDGE (2.5G) networks have maximum data rates of 171.2kbps and 384kbps, respectively. On the other hand, as illustrated in the figure below, the data rate for 3G/3.5G wireless standards, such as CDMA2000 and WCDMA with High-Speed Downlink Packet Access (HSDPA), can require a throughput of 10Mbps or more in order to support multimedia rich content. Figure 3: Data Rate Requirements for Wireless Standards From the chart above, it is apparent that neither UART and SPI throughput (~1Mbps) cannot satisfy the demanding bandwidth of 3G/3.5G wireless networks. An interesting fact about USB (Full-Speed) interfaces available in today s mobile wireless processors is that they offer a theoretical bandwidth of 12Mbps. One would think this could satisfy the 3G/3.5G throughput requirement; however, with protocol overhead the effective

4 bandwidth may be less than 2Mbps (according to test results obtained from a major mobile handsets manufacturer). Moreover, as the USB host port needs to be active at all times, this translates into power consumption even when no real data is passed through the interconnect channel. Furthermore, USB s high power consumption is another shortcoming that impacts its use as an IPC mechanism. Thus, none of the existing serial interfaces can provide sufficient data rates for a 3G/3.5G wireless handset solution. Moreover, the limited number of available USB ports on the processors can also prevent it from being used for IPC, as USB ports are also required for PC and peripheral connections. Since the conception of the 3G/3.5G wireless network standards, smartphone and PDA mobile handset designers have been struggling to search for an efficient processor interconnect solution. Many of the new designs include using a combination of the existing serial standards, thus creating multiple data lanes that pump data from one processor to the other. Although this may seem like a feasible solution, the software that is needed to handle this type of data flow becomes extremely complicated and prone to integrity issues. As these mobile handset designs are time critical and their time-tomarket determines a big chunk of their success, system designers cannot afford to lose time worrying about inter-processor communication. Another solution that has been explored is using a CPLD to interconnect the two processors. The problem with this approach is four-fold. First, the CPLDs need to be programmed, which takes more development time and resources. This introduces unnecessary complexity to the system design. Second, CPLDs usually take up more board space than other approaches, as these devices are not optimized for mobile applications. Third, CPLDs increase the overall bill of materials (BOM), as it is in fact a complicated piece of silicon and its cost can increase with the addition of development boards and other miscellaneous development costs. Lastly, CPLDs usually consume more power than more application-specific devices. Thus, using a CPLD for IPC is far from a simple approach and it can potentially be detrimental to mobile handset designs. Low-Power Dual-Port for Inter-Processor Communication (IPC) Low-power dual-port memory as a system interconnect implementation has recently emerged in the mobile handset space. Dual-port memories provide high-bandwidth throughput that will be able to meet the needs of even next generation wireless data rates. At the same time as providing high effective bandwidth, dual-port memories maximize battery life by keeping consumption at a minimum compared to serial interfaces. Interfacing across a dual-port memory is also a straightforward process and employs mechanisms that designers are already familiar with. Memory interfaces are standard interfaces that connect seamlessly to off-the-shelf processors. Additionally, no complex device drivers are required, as the interface is memory mapped between the processors, further simplifying software development and shortening product time to market. Hardware interrupts provide a simple mechanism for processor handshaking, offering substantial efficiency and minimal protocol overhead for managing the communications link when compared to interfaces such as USB. This reduced overhead also conserves

5 power by not requiring the processors on either sides of the link to maintain a heavy/thick and cycle-hungry protocol stack that also introduces unnecessary store and load operations. The overall efficiency of low-power dual-port IPCs has been further evaluated, as the effective throughput rather than the theoretical throughput is always the concern of handset architects and designers when evaluating IPCs. To measure the effective throughput, Cypress and TI have developed a platform comprising two Texas Instruments OMAP1710 application processors with the Cypress low-power MoBL dual-port (CYDM256B16). The hardware setup is shown in Figure 4. Figure 4: MoBL Dual-Port Evaluation Platform Hardware Setup The software is developed on a Symbian 8.1 EKA1 OS platform, and a simple nondouble/rotational buffered hardware interrupt scheme is used for handshaking. The throughput is calculated based on bursting data from the server to the client processor, with a preset packet size. Different packet sizes have been used to benchmark the effective throughput of the system, which varies with hardware interrupt frequency. The throughput performance can potentially improve with double/rotational buffer implementation; however, a more conservative approach has been taken to simply software as well as minimizing the number of interrupts generated. The results are tabulated in Table 1 and plotted in Figure 5. Table 1: Throughput Summary Packet Size Throughput 8kB (4k x 16) 50 Mbps 4kB (2k x 16) 48 Mbps 2kB (1k x 16) 31 Mbps 1kB (512 x 16) 19 Mbps 512B (256 x 16) 10 Mbps

6 60 MoBL Dual-Port Effective Throughput vs. Packet Size 50 Throughput (Mbps) x16 512x16 1kx16 2kx16 4kx16 Packet Size Figure 5: Effective Throughput with Different Packet Sizes For example, consider a Full-Speed USB interconnect implementation compared to a dual-port interface transferring a 1Mbit multi-media file from the baseband processor to the application processor. A USB interface with an effective throughput of 2Mbps will take 0.5s for the file to be completely transferred (1Mb / 2Mbps = 0.5s). This also has the effect that both serial interfaces on both processors need to be awake for the duration of this data transfer with the relevant power consumption. On the other hand, a lowpower dual-port implemented as the processor interconnect will require only 0.02s for the 1Mb file to be transferred at 48Mbps (1Mb / 48Mbps = 0.02s). Moreover, the dual-port and the other processor can automatically go into sleep mode after the data has been transferred. This reduces the time that both processors are burning power by over 96%, a significant power savings. Not only does a low-power dual-port interconnect provide superior performance and power consumption compared to other alternative mechanisms, it also comes in an ultra compact vfbga package that minimizes the board space requirement. Other features of low-power dual-ports, such as the input read and output drive registers, can also offload precious GPIO usage on the processors. This is illustrated in the figure below. Figure 6: Input Read Register and Output Drive Register Usages

7 The proliferation of 3G/3.5G wireless networks, multimedia rich content boosts the interprocessor communication bandwidth requirement of portable devices significantly. As a result, the use of conventional serial interfaces (UART, SPI, and Full-Speed USB) becomes insufficient and ineffective in 3G/3.5G applications that must transport real-time video, music, games, etc. Low-power dual-port memory serving as an interprocessor connection not only offers high-bandwidth and low-power consumption that satisfies stringent design requirements, it also provides a wide range of features that can simplify software and hardware designs and, in many cases, provide the best way to handle interprocessor communication in next generation mobile handsets.

8 Authors Biography: Danny Tseng is a Senior Applications Engineer in the Data Communications Division at Cypress Semiconductor. He received a Bachelor of Applied Science in Honors Electrical Engineering with Management Science option from the University of Waterloo in Lawrence Wong is a Member of Group Technical Staff in the Wireless Application Team at Texas Instruments. He received a Master of Science in Electrical Engineering in 1990 and a Bachelor of Science in Electrical Engineering in 1988 from the University of Southern California. Hung Vuong is a Senior System Architect and Systems and Software CTO for the Cellular Systems, Wireless Terminals Business Unit at Texas Instruments. He received Bachelor of Science in Electrical Engineering in 1988 from the University of Central Florida. Trademarks: Palm Treo is a trademark of Palm, Inc., Symbian is a trademark of Symbian, Ltd, Windows is a trademark of Microsoft Corporation, Wi-Fi is a trademark of the Wi-Fi Alliance, Bluetooth is a trademark of the Bluetooth SIG, MoBL is a trademark of Cypress Semiconductor Corporation, and OMAP is a trademark if Texas Instruments. All other trademarks and registered trademarks are property of their respective owners.