How to Solve DDR Parametric and Protocol Measurement Challenges

Transcription

1 How to Solve DDR Parametric and Protocol Measurement Challenges Agilent DTD Scopes and Logic Analyzer Division Copyright 2008 Agilent Technologies Solve DDR Phy & Protocol Challenges Page September 2008 Agenda Brief review of DDR market (uses for DDR DRAMs) New Agilent solutions to improve accuracy and speed to insight for DDR memory debug Debug challenges with DDR and where Agilent can help Physical layer electrical characterization and compliance Functional verification protocol and cross-bus correlation Summary of Agilent s DDR digital test solutions Page 22 Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 DDR Parametric & Protocol Meas. 1

2 Where Are DDR DRAM Usually Found? Embedded Designs for HDTV encoder board, printers and phones, projectors etc. SO-DIMM (Small Outline Dual In-line Memory Module) for Mobile PC FPGA Design DDR DRAM DIMM (Dual In-line Memory Module) for Regular PC Page September 2008Month ##, 200X DDR Memory Used Everywhere Easily recognized applications Workstations Actually very broad utilization Photocopy Machine Fax Machine Desktop Video Games Refrigerator High Definition TV Hi-Fidelity System HD-DVD/Bluray Home Entertainment System VOIP Phone Servers Projector Networking Equipment Printer Tablet PC Automobile Communication Systems Agilent Test Equipment Page 44 Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 DDR Parametric & Protocol Meas. 2

3 Agenda Brief review of DDR market (uses for DDR DRAMs) New Agilent solutions to improve accuracy and speed to insight for DDR memory debug Debug challenges with DDR and where Agilent can help Physical layer electrical characterization and compliance Functional verification protocol and cross-bus correlation Summary of Agilent s DDR digital test solutions Page 55 Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 Probing Requirement for DDR Validation Memory Controller DRAM Ideal Probing Points DRAM Ballout DIMM PCB trace DIMM Connector Above is a general DDR memory architecture. JEDEC defines the DDR spec at the DRAM ballout. To fully comply with the specification, probing is recommended to be made at the DRAM ballout for most accurate results. Page 6 Solve DDR Phy & Group/Presentation Protocol Challenges Title 25 September Month September ##, X DDR Parametric & Protocol Meas. 3

4 Probing Options and Issues for Oscilloscope Probing at the center of the trace DRAM Memory Controller Many engineers will find other alternative points to probe at the DDR signals. One example above is probing at the transmission line or surface mount components. However, there is a risk of signal reflection and other signal integrity issues. Page 7 25 September Month ##, X Confidence in Measurements Probe position on series-terminated transmission line At balls of the BGA (receiver) At mid-bus (non-ideal) Application Note Page 8 25 September Month September ##, X DDR Parametric & Protocol Meas. 4

5 Issues with Current Embedded Probing Solutions on Logic Analyzer Complete Protocol validation with the logic analyzer requires access to many signals (daunting task for flying leads). Other design-in probing methods fail to get close enough to the end of the transmission line or only access DDR signals via a DIMM slot probe Flying leads and mid-bus probing methods are sometimes not practical for boards with tight board space constraints (especially on an embedded system) Flying leads probing Page 99 Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September Month ##, 200X 2008 DDR 2/3 BGA Probes Probing directly at the ball-out of the DRAM For oscilloscopes and logic analyzers Page September Month September ##, X DDR Parametric & Protocol Meas. 5

6 Introducing World s First W2630A Series DDR2 and DDR3 BGA Probe Adapters DDR2 BGA Probe Adapter for Scope and Logic Analyzer DDR3 BGA Probe Adapter for Scope Key Features and Benefits: Easiest way to access your DDR signals Superior signal integrity probing for most accuracy in measurement W A W A Compatible with scope and logic analyzer probes Page Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 Ideal Probing with DDR2/3 BGA Probe Adapters DDR2 BGA Probe Adapter for Scope and Logic Analyzer DDR3 BGA Probe Adapter for Scope Logic Analyzer Probe Scope Probe Tip Page 12 Scope Probe DDR2 and DDR3 BGA probe adapters provide signal access points for scope and logic analyzer probing. Month ##, 200X DDR Parametric & Protocol Meas. 6

7 Ideal Probing with DDR2/3 BGA Probe Adapters 1. Solder DDR2 device to BGA Probe 2. Solder BGA Probe to DUT Board 3. Attach ZIF Probe to DDR2 BGA Probe 4. Attach ZIF Probe to Logic Analyzer Cable Page September 2008Month ##, 200X Superior signal integrity probing with embedded resistors in BGA probe Probe Here DRAM Probe Here DDR2/3 BGA Probe PCB Embedded Resistors Embedded resistor provides isolation of the probe loading and the live signal. Page 14 Embedded resistor isolates the probe loading effect from the signals. 25 September Month ##, X DDR Parametric & Protocol Meas. 7

8 Superior signal integrity probing for most accuracy in measurement Sample Test Results from Key DRAM Company on the BGA probe Engineer s Quote: These attenuations of waveforms are acceptable and comprehensible. Therefore, the BGA probe can be used for the measurements. Without BGA Probe With BGA Probe Probing directly at the signals and BGA probes yield similar results. Page September Month ##, X BGA Probing Saves Space And Potentially Test Cycles Final Released Product Confirm/correlate on final release layout Validation/Reference Design Connector? Where? If you don t t have the BGA Probe Validate on larger layout There is no space for my probe footprint? Probing here, ok. But how does that relate back to the final released product?? Page September 2008Month ##, 200X DDR Parametric & Protocol Meas. 8

9 BGA Rework Service If you need someone to provide you with the BGA attachment service, you can contact Circuit Rework. They have successful attached the DDR BGA probes. Company webpage: Rework conditions and charges (information may change, contact Circuit Rework) Solve DDR Phy & Protocol Challenges Page September 2008 DDR2/3 BGA Probe Solution - Pieces and Parts DDR2 BGA Probe Adapter for Logic Analyzer and Scope W2631A W2632A W2633A W2634A E5384A E5826A DDR2 x16 BGA command and data probe (4 units) DDR2 x16 BGA data probe (4 units) DDR2 x8 BGA command and data probe (4 units) DDR2 x8 BGA data probe (4 units) 46-ch single-ended ZIF probe for x8/x16 DRAM BGA probe, req s 90-pin LA cable 46-ch single-ended ZIF probe for x16 DRAM (data only) BGA probe, req s 90-pin LA cable E5827A 46-ch single-ended ZIF probe for 2 x8 DRAM (data only) BGA probe, req s 90-pin LA cable 1130/60A InfiniiMax probe amplifier N5424A/25A ZIF probe head and tips N5381A Solder-in probe head DDR3 BGA Probe Adapter for Scope W2635A-010 x8, 10 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units) W2635A-011 x8, 11 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units) W2636A-010 x16, 10 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units) W2636A-011 x16, 11 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units) 1130/60A InfiniiMax probe amplifier N5424A/25A ZIF probe head and tips N5381A Solder-in probe head Page September 2008Month ##, 200X DDR Parametric & Protocol Meas. 9

10 Agenda Brief review of DDR market (uses for DDR DRAMs) New Agilent solutions to improve accuracy and speed to insight for DDR memory debug Debug challenges with DDR and where Agilent can help Physical layer electrical characterization and compliance Functional verification protocol and cross-bus correlation Summary of Agilent s DDR digital test solutions Page Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 DDR Design & Simulation using Advanced Design System Driver/Receiver Design and Optimization DDR channel simulation Interconnect Modeling Automated DDR Measurements Design for interoperability Package Simulation for SI and PI Physical Design Verification Solve DDR Phy & Protocol Challenges Page September 2008 DDR Parametric & Protocol Meas. 10

11 DDR Automated Measurements Saves Time Issue: I need to spend a lot of effort and time to manually characterize the huge list of electrical and timing performance parameters from the JEDEC specifications, and then record the results into the test report. I cannot exhaustively characterize the test parameters. Solution: The oscilloscope DDR compliance test applications provide automated measurements for DDR 1, 2 and 3 as well as Low Power DDR specifications. The results are summarized in an automatically generated HTML report. Solve DDR Phy & Protocol Challenges Page September 2008 Example of Automated Measurements Eye-Diagram Analysis Write Preamble Width DQ Setup Time Falling Edge Slew Rate Page 22 Month ##, 200X DDR Parametric & Protocol Meas. 11

12 Clock Jitter Failures Issue: What are the available tools that can help me quickly and effectively troubleshoot jitter issues? Solution: The oscilloscope EZJIT and EZJIT-Plus tools are able to help you identify the source of your jitter so you can fix these issues effectively. To ensure the DDR clock meets the JEDEC specification for jitter, you can use available automated tools. However, how do you troubleshoot and identify the root cause if the clock fails some of the jitter tests? Clock Jitter Failures Automated DDR Clock Jitter Analysis Tool Page September Month ##, X Troubleshooting Clock Jitter Issues (1) You can use a generic jitter tool for troubleshooting by looking at the spectrum of the jitter error trend. DDR Clock Signal Clock Jitter Error Trend FFT of Error Trend (Observe and measure the frequency of the spikes) The jitter are coupled by onboard oscillators. Page September Month ##, X DDR Parametric & Protocol Meas. 12

13 Troubleshooting Clock Jitter Issues (2) To observe low frequency jitter component, the error trend can be smoothen out. You can observe and measure the low frequency oscillation. The frequency is 202kHz which is caused by switching power supply coupled to the DDR clock signal. Page September Month ##, X Troubleshooting Clock Jitter Issues (3) Measured power switching supply Clock Jitter Error Trend Comparing the smoothen clock jitter trend with signals like power line, you can correlate the clock jitter with power switching line. Page September Month ##, X DDR Parametric & Protocol Meas. 13

14 DDR Eye-Diagram Analysis Similarly to the automated clock jitter analysis, there are tools that can automatically help you analyze the Read and Write eye-diagram. Define your own mask to quickly check the signal integrity performance Page September Month ##, X DDR Eye-Diagram Analysis Issue: How do I troubleshoot an eye-diagram failure when it violates the DDR mask? Solution: The mask unfolding feature of the oscilloscope is able to pinpoint the exact failure location of the violation and allows navigation to any of the failure position. You can then perform more failure analysis such as measuring the timing relationships between signals or look at DQ pattern for intersymbols interference (ISI) related failures. Eye diagram failure Unfold Read Time Eye Navigate to any failure position by clicking on the arrow buttons Page September Month ##, X DDR Parametric & Protocol Meas. 14

15 Further Analysis after Mask Unfolding Measure the timing relationship between signals (such as Clock and DQS signals) Measure signal integrity Rise/fall time Slew rate Amplitude Overshoot/Ringing Find patterns on DQ signals for ISI related problems. Use Mask Unfolding to debug your DDR Signals Page September Month ##, X How do you track infrequent errors? Issue: Can you effectively track these infrequent occurrences? 1. A glitch that happens once every 5 minutes. 2. Signal overshoot due to crosstalk when the adjacent channel transition. 3. ISI failure due to specific DQ pattern. Press Single button until you get it? Shouldn t our job be spent on more meaningful work? Page September Month ##, X DDR Parametric & Protocol Meas. 15

16 Capture Infrequent Errors with InfiniiScan Zone Trigger Solution: If you can see it, you can trigger on the signal anomalies with the zone trigger. Just draw the zone where you see the glitch and scope will trigger only when the glitch appears. You can also set zone to trigger at signal overshoot. Page 31 Month ##, 200X Track Specific Pattern with InfiniiScan Zone Trigger Using InfiniiScan, you re now trigger on pattern Page Month ##, 200X DDR Parametric & Protocol Meas. 16

17 Agenda Brief review of DDR market (uses for DDR DRAMs) New Agilent solutions to improve accuracy and speed to insight for DDR memory debug Debug challenges with DDR and where Agilent can help Physical layer electrical characterization and compliance Functional verification protocol and cross-bus correlation Summary of Agilent s DDR digital test solutions Page Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 Functional Validation Challenges Signal Integrity issues create inaccurate timing and protocol measurement. We need to be able to access and analyze all the buses at the same time to perform a quick signal integrity check. Read and write data capture for protocol analysis. We need to be able to sample at the correct sampling position on both read and write data valid window to enable accurate state capture. Spending a lot of time on the work bench, trying to analyze the raw command, bank address and read/write data from the captured trace. Solve DDR Phy & Protocol Challenges Page 34 Page September 2008 DDR Parametric & Protocol Meas. 17

18 EyeScan Feature for Quick SI Check Issue: Probing every command, address, control and data line to check SI issues with oscilloscope can be tedious. Solution: EyeScan with logic analyzer gives a superior and quick SI insight into all the memory buses simultaneously. Clear eye opening suggests good SI Oscilloscope provides single channel high resolution eye diagram Adjust threshold and sampling position for accurate data capture Bad bit found (inactive data line) EyeScan with logic analyzer result on multiple DDR channels for quick SI glance Solve DDR Phy & Protocol Challenges Page 35 Page September 2008 Dual Sample Mode for Read and Write data sampling Issue: Sampling DDR2 signals with Read and Write data at a 90 degrees out of phase. Solution: 16950B has dual sample mode capability which allows Read and Write data to be sampled at 2 different sample times as specified in the DDR JEDEC specification. Read data Write data Write data is center aligned with clock edge Dual Sample mode architecture in 16950B Read data is edge aligned with clock edge Solve DDR Phy & Protocol Challenges Page 36 Page September 2008 DDR Parametric & Protocol Meas. 18

19 Protocol Decode Tool Issue: Analyzing each bit for functional validation with Timing waveform window is time consuming. Solution: Protocol decode provides protocol decode information in an intuitive format. Protocol decode: Decodes command, Address, Burst type, Data.. Etc (First data burst reading 0xEE6A) Timing Waveform : Valid command at READ with first data burst reading 0xEE6A Solve DDR Phy & Protocol Challenges Page 37 Page September 2008 Troubleshooting Cross-Domain DDR Memory Failures (Digital Analog) If a write to a particular address (or range of addresses) in memory is consistently corrupt, how can I trigger an oscilloscope on a write command to the specific address? What if I want to measure a JEDEC timing parameter with the oscilloscope, but I need to qualify the measurement with a specific DDR command? I need more oscilloscope inputs!! But, even with more oscilloscope inputs, I wouldn t have the powerful capabilities of a logic analyzer trigger. Help!!! Page September 2008Month ##, 200X DDR Parametric & Protocol Meas. 19

20 Using ViewScope to Correlate Scope and Logic Analyzer DDR Measurements Combine the triggering, memory and digital bus acquisition power of a logic analyzer with the analog measurement capability of an oscilloscope. Great for tracking functional failures to root cause (jitter, cross-talk, EMI, etc) Page September 2008Month ##, 200X Using ViewScope for Cross Bus Correlation Infiniiscan zone qualify send output trigger to from scope to logic analyzer Command LDQS Data value DQ 0 Address value Command DQ scope waveform Data Obtain corresponding multiple memory bus information from a single DQ 0 bus: Read Command at Address 0420 with data 0800 Address Page September 2008Month ##, 200X DDR Parametric & Protocol Meas. 20

21 Agenda Brief review of DDR market (uses for DDR DRAMs) New Agilent solutions to improve accuracy and speed to insight for DDR memory debug Debug challenges with DDR and where Agilent can help Physical layer electrical characterization and compliance Functional verification protocol and cross-bus correlation Summary of Agilent s DDR digital test solutions Page Solve DDR Phy Group/Presentation & Protocol Challenges Title 25 September 2008Month 25 September ##, 200X 2008 DDR Logic Analyzer Solutions 16902B Logic Analyzer Mainframe NEW!! Generation Module Probes (DIMM, SO-DIMM, Embedded) DDR 1 DDR /1B 16950/1B FuturePlus FS2336 Interposer FuturePlus FuturePlus FS2332/4 Interposers FuturePlus FS2333 SO-DIMM Probe FuturePlus FS2333 SO- DIMM Probe Flying Leads NEW!! W2630A Series DDR2 BGA Probes Soft Touch Soft Touch DDR 3 Please contact your local Agilent Sales Representative Page September 2008Month ##, 200X DDR Parametric & Protocol Meas. 21

22 DDR Scope Solutions Infiniium 8000 and Series Oscilloscopes InfiniiMax Probing Solutions W2630A Series DDR2 and DDR3 BGA Probes N5414A InfiniiScan for Easy Read/Write Separation Solve DDR Phy & Protocol Challenges Page September 2008 DDR Resources Agilent DDR Solution Central Webpage DDR2 BGA Probe Solutions DDR3 BGA Probe Solutions Logic Analyzer Oscilloscopes Scopes DDR 1, 2 and 3 Automated Software Packages: DDR1: DDR2: DDR3: DDR Design Solutions DDR Application Note: Solve DDR Phy & Protocol Challenges Page September 2008 DDR Parametric & Protocol Meas. 22