ENVISION TECHNOLOGY CONFERENCE. Functional intel (ia) BLA PARTHAS, INTEL PLATFORM ARCHITECT

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1 ENVISION TECHNOLOGY CONFERENCE Functional intel (ia) BLA PARTHAS, INTEL PLATFORM ARCHITECT

2 Legal Notices & Disclaimers This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Statements in this document that refer to Intel s plans and expectations for the quarter, the year, and the future, are forwardlooking statements that involve a number of risks and uncertainties. A detailed discussion of the factors that could affect Intel s results and plans is included in Intel s SEC filings, including the annual report on Form 10-K. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate. Intel, the Intel logo, Pentium, Celeron, Atom, Core, Xeon and others are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others Intel Corporation. Intel Proprietary

3 THE KEY TILES OF INTEL S FUSA STRATEGY Design for Safety HW features for Fusa, Safety Island FuSa process Platform and SW level FuSa FuSa E2E & selfadaptable systems

4 SOLUTIONS FOR INDUSTRIAL FUSA

5 BENEFITS OF SYSTEM CONSOLIDATION Low solution BOM cost Simple to secure Small system equipment footprint Few devices to manage Low system/factory integration complexity and maintenance Outstanding Reliability

6 INTEL XEON PROCESSOR D- 1529

7 INTEL XEON PROCESSOR D-1529 FOR INDUSTRIAL IEC CERTIFICATION Why? ALLOWS CONSOLIDATED SOLUTIONS WITH MIXED CRITICALITY WORKLOADS (SAFE & NON SAFE TOGETHER) IA APPROACH ALLOWS SCALABILITY AND REUSE. SHORTENS DEVELOPMENT AND CERTIFICATION TIME SCALE APPLICATION AS SAFETY ATTACH-RATE INCREASES Thousand Oaks Configuration BDX-DE PLATFORM (D C, 1.3GHZ SKU) SW TEST LIB IS RTOS AND H/V AGNOSTIC. SUPPORT MULTIPLE RTOS VENDORS S/W DIAGNOSTICS INVOKED FROM SAFETY APPLICATION Out of Context Compliant IC Safety Collateral Safety Diagnostic Library

8 INTEL XEON D PROCESSOR SAFETY SKU D-1529 CPU 4 Core Intel Xeon (14nm) CPUs L1 cache 32K data, 32k instruction per core L2 cache 256K per core LLC cache 1.5Mb per core with QoS Frequency 1.3GHz TDP <<20W Memory DDR4 up to 1600 MT/s DDR3L up to 1600 MT/s Two Channels (2 DIMMs/Channel) Safety Fusing SW Test Lib will only operate on safety SKU Reliability Industrial Use Case: 24x7x10 Years; 105 C T jmax, 60 C Ambient PCI-E* x24 PCIe Gen3 (locked at Gen2 speed) with up to 6 controllers DDR3L-1600 DDR Intel Ethernet 2x10 GbE SATA 3.0 x2 DMA PCU DDR3L-1600 DDR BDW Core BDW Core PCIe Gen3 24 Lanes, 6 Controllers BDW Core BDW Core LLC LLC LLC LLC Integrated IO x4 USB 2.0 and x2 SATA 3 Technologies VT-x2, VT-d, Core RAPL, PECI over SMBUS Package FCBGA, Ball Pitch: 0.7 mm minimum (balls anywhere) Dimension: 37.5 mm x 37.5 mm Clocks USB 3.0 x4 USB 2.0 x4 PCIe Gen2 8 Lanes 8 Controllers Legacy I/O Legacy I/O SPI for boot flash, SMBus, UART LPC, GPIO, 8259, I/O APIC, 8254 Timer, RTC

9 SOFTWARE ARCHITECTURE S/W Test Lib PROVIDES ADDITIONAL D/C VMM and RTOS agnostic API s allow customer to invoke and interrogate diagnostic functions SAME API FOR NEW GENERATIONS

10 WRS SOFTWARE DOCS SILICON DELIVERABLES BDX-DE D-1529 SKU New MM# New CPUID Safety Fuse set Safety Manual etc Includes link to IRC landing page S/W Diagnostic Library One time download per customer Will only run on FuSa SKU Wind River Vx7 Safety Profile Run Time License (potential to include cert BSP)

11 SUMMARY Intel s Functional Safety solutions enable 1. Fewer and lower cost development cycles due to mixed criticality approach 2. Faster certification time 3. Scalability and reuse 4. A rich ecosystem offering standard form factor functional safety modules

12 THANK YOU!