Strategy overview STACY J. SMITH GROUP PRESIDENT, MANUFACTURING, OPERATIONS AND SALES SEPTEMBER 19, 2017 TECHNOLOGY AND MANUFACTURING DAY

Transcription

1 Strategy overview STACY J. SMITH GROUP PRESIDENT, MANUFACTURING, OPERATIONS AND SALES SEPTEMBER 19, 2017

2 Legal Disclaimer DISCLOSURES China Tech and Manufacturing Day 2017 occurs during Intel s Quiet Period, before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year s program. Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, goals, plans, believes, seeks, estimates, continues, may, will, would, should, could, and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company s expectations are set forth in Intel s earnings release dated July 27, 2017, which is included as an exhibit to Intel s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel s results is included in Intel s SEC filings, including the company s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at or the SEC s website at

3

4 The number of transistors and resistors on a chip doubles every 24 months -Gordon Moore Two Implications: 1. Cost per square millimeter goes up over time 2. Doubling of transistors = Scaling Improves performance Cost per transistor declines

5 What if Moore s Law is applied to Transportation? Agricultural productivity? Terracotta Warriors? We could travel to the Sun on a single gallon We could feed the world s population with 1km 2 of land We could build 64 billion warrior statues Source: Intel Internal Analysis.

6 Is Moore s Law dead?

7 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm Is moore s law dead? NO! mm 2 / Transistor (log scale) $ / mm 2 (log scale) $ / Transistor (log scale) Source: Intel

8 The time between nodes has lengthened Are you Getting the same Moore s Law benefit?

9 YES! Because we are getting more scaling

10 We Are Hyper Scaling (on 14 nm & 10 nm) Hyper scaling enables us to achieve accelerated density improvement Intra-node optimizations enable an annual cadence of product enhancements

11 Microprocessor die area scaling 100 mm x 62 mm x Area 38.4 mm x 0.43x IO Logic IO Logic IO Logic 17.7 mm mm 2 SRAM 100 SRAM mm SRAM mm 2 IO Logic 100 SRAM mm 2 IO Logic 100 SRAM mm 2 45 nm 32 nm 22 nm 14 nm 10 nm Hyper scaling delivers better than 0.50x die area scaling on 14 nm and 10 nm Source: Intel

12 Moore s Law Translates to Lower Product Costs 22 nm & 14 nm Client Cost Curves (Launch + 5 quarters) $ Ivybridge Broadwell Haswell Skylake 0 Kabylake Q2'12 Q2'13 Q2'14 Q2'15 Q2'16 Q2'17 Source: Intel

13 $/MTX 90nm Moore's Law in action PC CPU Weighted Average Cost Per Transistor ($/MTX) (log scale normalized to 90nm) 65nm 45nm 32nm 22nm 14nm Q2'04 Q2'05 Q2'06 Q2'07 Q2'08 Q2'09 Q2'10 Q2'11 Q2'12 Q2'13 Q2'14 Q2'15 Q2'16 Q2'17 Source: Intel

14 Gross Margins Gross Margin % Annual F 70% 65% 60% 55% 50% 45% 40% F 2016 and 2017 forecasted figures are on a non-gaap basis. Refer to Intel s earnings release for a reconciliation of these non-gaap measures at forecasts are Intel estimates, based upon current expectations and available information and are subject to change without notice. Source: Intel

15 Competitors are announcing10nm this year Have you lost your lead?

16 LOGIC AREA (relative) 14nm Is ~3 years ahead 1 45nm 40/45nm 32nm 28nm Others 20nm nm 14/16nm 3 years 10nm Intel 14nm 10nm HVM WAFER START DATE Source: Intel

17 Our Scale

18 Investment Required to Build & Equip A Leading Edge Wafer Factory ~$10b

19 Si technology is becoming rare 25 Mitsubishi Sanyo Rohm ON Hitachi Atmel ADI Sharp Cypress Sony Infineon TI Toshiba Freescale SMIC Renesas Fujitsu Panasonic UMC ST-M IBM AMD Samsung TSMC Intel NUMBER OF PLAYERS WITH A LEADING EDGE LOGIC FAB 18 Sharp Cypress Sony Infineon TI Toshiba Freescale SMIC Renesas Fujitsu Panasonic UMC ST-M IBM AMD Samsung TSMC Intel TI Toshiba SMIC Renesas Fujitsu Panasonic UMC ST-M IBM GF Samsung TSMC Intel TI Toshiba SMIC Renesas Fujitsu Panasonic UMC ST-M IBM GF Samsung TSMC Intel 8 Panasonic UMC ST-M IBM GF Samsung TSMC Intel 5 IBM GF Samsung TSMC Intel 4 GF Samsung TSMC Intel 02-'03 04-'06 06-'08 08-'12 10-'12 12-'14 14-'16 (130nm) (90nm) (65nm) (45/40nm) (32/28nm) (22/20nm) (16/14nm) Other names and brands may be claimed as the property of others. Note: GF relies on Samsung s process recipe for 14nm. GF-IBM Fabs acquisition announced in 2014 Source: Analyst reports; company information

20 Fab and Assembly Test Sites Arizona Oregon New Mexico Ireland Israel Dalian Chengdu Vietnam Penang Kulim Wafer Fabs Assembly Test

21 Global Manufacturing By the Numbers INTEL EMPLOYEES MANUFACTURING SPACE TRANSISTORS ~30K +4M SQUARE FEET +10B MANUFACTURED OF CLEANROOM PER SECOND Source: Intel 28

22 China Footprint Intel China Jobs Total Capex Invested +7K +$13B Since Year History in China with World Class Fab and Assembly Test Facilities Source: Intel

23 Announcing First Commercially available 64-Layer Intel 3D NAND SSD for the DatA Center!!

24 world class supply chain 2017 MASTER Apple / P&G / Amazon 1. Unilever 2. McDonald s 3. Inditex 4. Cisco Systems 5. H&M 6. Intel 7. Nestle 8. Nike 9. Colgate-Palmolive 10. Starbucks

25 Caring for the environment Reducing waste, water and carbon footprint Inspiring employees, shareholders, customers

26 Awards and Recognitions

27 Intel Custom Foundry

28 57_84 The opportunity ~ Leading edge foundry market is Growing FOUNDRY TAM ($B) $30B Lagging Nodes $23B Leading Edge Note: Source: Samsung and Intel internal are excluded from TAM. Leading edge defined as: 65nm and below for 2010, 45nm and below for 2011 and 2012, 32 nm and below for Amalgamation of analyst data and Intel analysis.

29 2016 Leading Edge Foundry Market LEADING EDGE FOUNDRY TAM BY NODE 2016 TAM ($B) $23B GROWING AT 14% (CAGR ) Note: Samsung and Intel internal are excluded from TAM. Leading edge defined as: 28 nm and below for Source: Amalgamation of analyst data and Intel analysis.

30 Putting It All Together We continue to advance Moore s Law resulting in significant product and cost benefits We continue to outpace the rest of the industry (~3 year lead on 14nm) Our scale is a unique competitive advantage We are building a foundry franchise

31 One More Thing...

32 Presenting 10 nm