End User Update: High-Performance Reconfigurable Computing

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1 End User Update: High-Performance Reconfigurable Computing Tarek El-Ghazawi Director, GW Institute for Massively Parallel Applications and Computing Technologies(IMPACT) Co-Director, NSF Center for High-Performance Reconfigurable Computing (CHREC) The George Washington University hpcl.gwu.edu

2 Paul Muzio s Outline! Performance What hardware accelerators are you using/evaluating? Describe the applications that you are porting to accelerators? What kinds of speed-ups are you seeing (provide the basis for the comparison)? How does it compare to scaling out (i.e., just using more X86 processors)? What are the bottlenecks to further performance improvements? Economics Describe the programming effort required to make use of the accelerator. Amortization Compare accelerator cost to scaling out cost Ease of use issues Futures What is the future direction of hardware based accelerators? Software futures? What are your thoughts on what the vendors need to do to ensure wider acceptance of accelerators? 2

3 Why Accelerators: A Historical Perspective Performance Vector Machines Massively Parallel Processors MPPs with Multicores and Heterogeneous Accelerators HPCC End of Moore s Law in Clocking! Hopes are in Architecture! Time 3

4 Which Accelerators? We considered HPRCs more than anything else To be addressed today We are increasingly using GPUs Some Cell 4

5 High-Performance Reconfigurable Computing (HPRC) 5 IEEE Computer, March 2007 High-Performance Reconfigurable Computers are parallel computing systems that contain multiple microprocessors and multiple FPGAs. In current settings, the design uses FPGAs as coprocessors that are deployed to execute the small portion of the application that takes most of the time under the rule, the 10 percent of code that takes 90 percent of the execution time.

6 Evaluated FPGA-Accelerated Systems Altix-4700 XD1 SRC- 6E Altix-350 SRC- 6 HC-36 6

7 An Architectural Classification for Hardware Accelerated High-Performance Computers El-Ghazawi et. al. The Performance Potential of HPRCs. IEEE Computer, February 2008

8 Uniform Nodes Non-Uniform System (UNNS) μp 1 μp N μp 1 μp N RP 1 RP N RP 1 RP N μp Node μp Node RP Node RP Node IN and/or GSM HPRC Examples: SRC 6/7, SGI Altix/RC100 Systems 8

9 Non-Uniform Nodes Uniform System (NNUS) μp RP μp RP IN and/or GSM HPRC Example: Cray XD1, Cray XT5h 9

10 Applications and Performance Cryptography, Remote Sensing and Bioinformatics

11 Hyperspectral Dimension Reduction Multi-Spectral Imagery 10 s of bands (MODIS 36 bands, SeaWiFS 8 bands, IKONOS 5 bands) Hyperspectral Imagery 100 s-1000 s of bands (AVIRIS 224 bands, AIRS 2378 bands) Challenges (Curse of Dimensionality) Solution Dimension Reduction Multispectral / Hyperspectral Imagery Comparison 11

12 Hyperspectral Dimension Reduction (Techniques) Principal Component Analysis (PCA): Most Common Method Dimension Reduction Complex and Global computations: difficult for parallel processing and hardware implementations Multi-Resolution Wavelet Decomposition of Each Pixel 1-D Spectral Signature (Preservation of Spectral Locality) Wavelet-Based Dimension Reduction*: Simple and Local Operations High-Performance Implementation * S. Kaewpijit, J. Le Moigne, T. El-Ghazawi, Automatic Reduction of Hyperspectral Imagery Using Wavelet Spectral Analysis, IEEE Transactions on Geoscience and Remote Sensing, Vol. 41, No. 4, April, 2003, pp

13 Wavelet-Based Dimension Reduction (Execution Profiles on SRC) Total Execution Time = sec (Pentium4, 1.8GHz) Total Execution Time = 1.67 sec (SRC-6E, P3) Speedup = x (without-streaming) Speedup = x (with-streaming) Total Execution Time = 0.84 sec (SRC-6) Speedup = x (without-streaming) Speedup = x (with-streaming) 13

14 Cloud Detection Band 2 (Green Band) Band 3 (Red Band) Band 4 (Near-IR Band) Band 5 (Mid-IR Band) Band 6 (Thermal IR Band) Software/Reference Mask Hardware Floating-Point Mask (Approximate Normalization) Hardware Fixed-Point Mask (Approximate Normalization) 14

15 15 G C T A T T G G - 0 G A T A C T T T - Protein and DNA Matching-The Scoring Matrix G C T A T T G G G A T A C T T T - 0 _ 1, _ 1,, 1 1, max, penalty gap j i F penalty gap j i F y x s j i F j i F j i

16 Application Smith-Waterman (DNA Sequencing) DES Breaker IDEA Breaker RC5(32/12/16) Breaker Savings of HPRC (Based on one Altix U rack) Speedup Cost Savings 22x 96x 2x 17x Assumptions 100% cluster efficiency Cost Factor P : RP 1 : 400 Power Factor P : RP 1 : U Rack: 1230 W µp board (with two µps): 220 W Size Factor P : RP 1 : 34.5 Cluster of 100 µps = four 19-inch racks» footprint = 6 square feet Reconfigurable computer (10U)» footprint = 2.07 square feet SAVINGS Power Savings 779x 3439x Tarek El-Ghazawi, GWU 16 HPC User Forum, Roanoke April 21, x 610x Size Reduction 253x 1116x 28x 198x

17 Smith-Waterman (DNA Sequencing) IDEA Breaker RC5(32/8/8) Breaker Hyperspectral Dimension Reduction Application DES Breaker Savings of HPRC (Based on one Cray-XD1 chassis) Speedup Cloud Detection 110 Assumptions 100% cluster efficiency Cost Factor P : RP 1 : 100 Power Factor P : RP 1 : 20 Cost Savings 28x 122x 24x 23x 1x 1x SAVINGS Power Savings 140x 608x 120x 116x Reconfigurable processor (based on one XD1 Chassis): 2200 W µp board (with two µps): 220 W Size Factor P : RP 1 : 95.8 Cluster of 100 µps = four 19-inch racks» footprint = 6 square feet Reconfigurable computer (one XD1 Chassis)» footprint = 5.75 square feet Tarek El-Ghazawi, GWU 17 HPC User Forum, Roanoke April 21, x 5x Size Reduction 29x 127x 25x 24x 1x 1x

18 Application Smith-Waterman (DNA Sequencing) DES Breaker IDEA Breaker RC5(32/12/16) Breaker Hyperspectral Dimension Reduction Cloud Detection 28 Assumptions 100% cluster efficiency Cost Factor P : RP 1 : 200 Power Factor P : RP 1 : 3.64 Savings of HPRC (Based on SRC-6) Speedup Cost Savings 6x 34x 3x 6x 0.16x 0.14x Reconfigurable processor (based on SRC-6): 200 W µp board (with two µps): 220 W Size Factor P : RP 1 : 33.3 Cluster of 100 µps = four 19-inch racks» footprint = 6 square feet SAVINGS Power Savings 313x 1856x 176x 313x Reconfigurable computer (SRC MAPstation TM ) Tarek El-Ghazawi,» footprint GWU = 1 square feet 18 HPC User Forum, Roanoke April 21, x 8x Size Reduction 34x 203x 19x 34x 0.96x 0.84x

19 Programming

20 Historical Perspective Technology In-Socket Accelerators (65 nm) Circuit Designers Users Tools Evolution New Methodologies, Programming Models and IDEs Platform Specifications & Parallel SW Languages Improved-HLLs Domain Scientists RC-Aware Domain Scientists Embedded Processors & Transceivers (90 nm) Embedded Software Engineers Embedded System Designers DSP Slice & Dual Port Block RAM (130 nm) HW/SW Codesign Embedded & DSP IDEs HLLs IP Core Generators HDLs Schematics RTL DSP & Networking Designers Logic Fabric (180 nm) HPRC PSoC Custom Comp. Glue Logic Glue Logic Applications Custom Comp. PSoC HPRC 20 Tarek El-Ghazawi, GWU 20 HPC User Forum, Roanoke April 21, 2008

21 Programming HPRCs 21

22 Productivity Analysis of Existing Tools Tools considered Impulse-C Handel-C Carte-C Mitrion-C SysGen RC-Toolbox HDLs Utility Frequency Area Cost Acquisition time Learning time Development time Results excerpted from GWU papers in SPL 07 and FPT 07 conferences. 22 Tarek El-Ghazawi, GWU 22 HPC User Forum, Roanoke April 21, 2008

23 Future Hardware Development More use of socket-based integration Better integration with memory hierarchy Better accelerators, in the FPGA side More computationally oriented/floating-point cores? Coarser grain FPGAs? On-chip FPGAs and accelerators? 23

24 Parallelism Concepts: From Systems to Commodity Chips Early 1970s First Vector and SIMD Systems CDC STAR-100 TI ASC ILLIAC IV First MIMD System CMU C.mmp (16 PDP11s) 1985 FPGA Xilinx 1998 HPRC SRC SIMD Altivec By Apple, IBM, and Motorola 2001 Vector Processor/ SIMD CELL BE GPGPUs NVIDIA and AMD Mulicore CPUs IBM Power 4 Time Coming soon? Hybrid- Reconfigurable/ Chip? Accelerators as cores? 24

25 Future Software More user/application-centric programming Unified parallel programming interface? More efficient compiling Tools for accelerator-gpp application co-design Virtualization for ease-of-use and portability HELP MAY BE COMING? 25

26 DARPA Studies DARPA is looking at bridging productivity gap for FPGAs NSF CHREC Schools (UF, GWU) and (BYU, VT) conducted a DARPA study DARPA has at least one more ongoing study Are we going to see any BAAs? 26

27 27

28 Conclusions Lots of common issues among accelerators For the applications that they can do well, they do really well! FPGAs were not built originally for computing Limited applications Less than user friendly interfaces Very long time for compiling Programming languages expose a restrictive view of the system and are often hardware oriented, Need a single system wide language paradigm A major bottleneck is data transfer rates between the microprocessor and the FPGA More work is needed on how to manage heterogeneity Virtualization for portability and ease of use Advanced programming models based on parallel computing New tools for performance tuning and debugging in heterogeneous environments Better integration into memory hierarchy The above requires fundamental work that will be unlikely supported by vendors alone, it needs a for example DARPA Driven Industry/University effort (like HPCS) Tarek El-Ghazawi, GWU 28 HPC User Forum, Roanoke April 21, 2008

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