SOI at the heart of the silicon photonics design. Arnaud Rigny, Business Development Manager Semicon Europa, TechArena

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1 SOI at the heart of the silicon photonics design Arnaud Rigny, Business Development Manager Semicon Europa, TechArena

2 Outline 1 Market demand for optical interconnect 2 Silicon on Insulator for optical integration 3 Silicon on Insulator, the industrial solution for mass market 4 Conclusion and roadmap for SOI 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

3 We are in the Data center era Communication matters 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena Source: Reuters, "Chanel Data Center", Karl Lagerfeld

4 1 Market demand for optical interconnect 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

5 IP trafic evolution 25% growth in trafic and 10% growth in communicating device 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena Source: Cisco Global Cloud Index,

6 Global Data Center Traffic by Destination (2019) Cisco Cloud index 2014 B C A Source: Cisco Global Cloud Index, /10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

7 Interconnection within data center Interconnection datarate is increasing : from 1Gb (2000) to 100G (2015) For speed of 10Gbs or higher For reach of 1km Source: Ethernet Alliance, 2016 Optical communication is the most efficient solution 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

8 Optical interconnect - Challenges Reach high data rate 40G in production 100G migration ongoing 400G next generation Need a scalable solution Cannot replace all fiber link from one generation to next generation Need cost/gb to decrease while data rate increase More high speed interconnect (new topologies) industrial solution to reach cost and volume requirements Silicon photonics can answer the challenges by Using the CMOS industry for mass production and low cost products Providing integrated platform for scalability Being compatible with Single Mode Fiber and WDM 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

9 Where to introduce optical interface 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

10 2 Silicon on Insulator for optical integration 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

11 Silicon material for optical transceiver Optical fiber has 3 main transparency windows : 850nm, 1.3µm and 1.55µm Silicon and optical fiber share the transparency windows: 1.3µm and 1.55µm 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

12 Waveguide with silicon on a planar surface As with the optical fiber, a wveguide in silicon needs a core and a cladding In silicon, the best material combination is Silicon (neff ~ 1.31/1.55µm) and SiO2 (neff = 1.55µm) To realize a waveguide on a planar structure, a planar SiO2/Si/SiO2 layer structure is needed Core Clad Core Clad Mechanical support (silicon, ) 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

13 From SOI wafer to photonics waveguide SOI wafer Blank SOI Si etching SiO2 cladding Back-end SOI wafer provides Two main kind of waveguide structure Monocristaline silicon wafer on top of thermal oxide (low loss propagation material) Thin and uniform silicon layer (accurate design) Material CMOS front end compatible Strip waveguide Ridge waveguide 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

14 From waveguide to devices Optical building blocks Integrated 4 channel WDM transceiver Grating coupler Laser integration Mach-Zender modulator Multiplexer Ring resonator modulator 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

15 Silicon photonics advantages compared to other solutions Integrated photonic device onto silicon, manufactured in a CMOS fab, enables low cost mass production Low loss propagation waveguide thanks to mono-crystalline top silicon layer Small devices thanks to high index contrast between Silicon and oxide Active device thanks to doping/back-end process Compatible with single mode fiber (SMF) Compatible with 1.3µm and 1.55µm optical windows Scalability to increase bit rate per channel and wavelength multiplexing Scalable solution to integrate optical transceiver close to the chip SOI is the platform of choice for silicon photonics 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

16 Some existing products in Silicon Photonics INTEL : 100G CWDM4 QSFP28 Optical Transceiver CISCO: 100G LR4 CPAK Luxtera : 100G (4x26) PSM4 QSFP Module Mellanox : 100Gb/s QSFP28 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

17 3 Silicon on Insulator, the industrial solution for mass market 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

18 SOI characteristics Wafer characteristics Diameter Defectivity Roughness Edge Crystal Thickness BOX thickness Handle Overall geometry Impact on Silicon Photonics CMOS node CMOS node Propagation loss Yield Propagation loss Yield Yield Propagation loss Yield 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

19 The Smart Cut process Oxidation Monocrystal silicon CMOS compatible All wafer size Thin silicon layer (<<1µm) SOI by Smart Cut Thermal oxide quality for BOX Very uniform silicon layer (<<10nm) Donor wafer becomes new wafer A Less than 2 wafer bulk for one SOI 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

20 SOI wafer key parameters Actual Mass production Diameter 200mm and 300mm 200mm and 300mm Defectivity (inspection threshold) 90nm (for 45nm CMOS node) 65nm (for 28nm CMOS node and beyond) Roughness 5A RMS (30x30µm²) 2Å RMS (30x30µm²) Edge <2mm Jagged edge <2mm smooth edge Crystal Mono crystal and poly Monocrystal Thickness 0,125µm - 0,5µm 3µm 0,125µm - 0,5µm 3µm Thickness control 10 nm 1 nm BOX thickness 1µm 2µm 3µm 1µm 2µm 3µm Handle Standard and high Ω.cm Standard and high Ω.cm Overall geometry warpage <80µm warpage <60µm 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

21 Thickness control for robust design Test device: grating coupler Used to evaluate impact of process variations Impact is measured by coupling efficiency variation (suppose the use of 4 wavelengths with 10nm spacing) SOI top layer thickness uniformity Simulation Variation of the minimum coupling efficiency with different SOI thicknesses variation Simulation by Daivid FOWLER CEA/LETI 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

22 SOI uniformity impact on overall process variation 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

23 SOI process and SOI uniformity CMP (polishing) process Thermal smoothing process Uniformity limit ~ 10nm Uniformity limit ~ 1 nm 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

24 Thermal smoothing principle Silicon surface smoothing at high temperature (RTA, BA) Material transport mechanism Bulk diffusion Evaporation / Condensation Surface diffusion Gas Evaporation / condensation Reaction with contaminant Surface diffusion Silicon Bulk diffusion Simulation of silicon smoothing under high temp anneal F.De Crecy CEA/LETI 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

25 Uniformity (+/- nm) SOI uniformity enabled by Smart Cut technology Yield improvement SOI uniformity map +/- 5Å SOI uniformity improvement and specification 6 5 Best wafer Spec Range Spec all point all wafers year Specification: Thickness uniformity of +/- 1nm all points all wafers 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

26 Roughness control for low propagation loss Standard surface roughness Advanced surface roughness Center 30x30µm² scan RMS = 2.2Å Center 30x30µm² scan RMS = 1.4Å Edge 30x30µm² scan RMS = 4.9Å Edge 30x30µm² scan RMS = 2Å Roughness RMS <5Å Roughness RMS <2Å 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

27 Edge quality strong improvement Jagged edge quality Smooth edge quality SOI Oxide Jagged silicon layer 360 edge measurement SOI Oxide Notch SOI terrace width : 800 to 1200µm Jagged edge Terrace width <2mm SOI terrace width : 800 to 1200µm Smooth edge Terrace width <2mm 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

28 Number of defects per wafer Excellent control of defectivity at low threshold Inspection (SP2) 65nm Pareto of defects bin cumulated >65nm >90nm >120nm Defect size 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

29 Photonics SOI wafer characteristics Ready for mass production Mass production requirement Diameter 300mm Defectivity 65nm Roughness 2Å RMS (30x30µm²) Edge <2mm smooth edge Crystal Monocrystal Thickness 0,125µm - 0,5µm Thickness control 1 nm BOX thickness 1µm-2µm Handle resitivity Standard Overall geometry warpage <60µm Validation 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

30 4 Conclusion 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

31 Conclusion 1. Silicon photonics is now a commercial reality 2. Volume for mass production will be mainly in 300mm 3. SOI wafer specs requirements are clear and Smart Cut technology enables industrial production 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

32 27/10/ SOI C2 / CONFIDENTIAL enables Semicon next Europa - Tech generation Arena data centers Source: Reuters, "Chanel Data Center", Karl Lagerfeld

33 Thank you for you attention 27/10/ C2 / CONFIDENTIAL Semicon Europa - Tech Arena

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