Power Aware Architecture Design for Multicore SoCs

Transcription

1 Power Aware Architecture Design for Multicore SoCs EDPS Monterey Patrick Sheridan Synopsys Virtual Prototyping April 2015

2 Low Power SoC Design Multi-disciplinary system problem Must manage energy consumption from software through to silicon Power Aware Architecture Design for Multicore SoCs User Persona: Architect Uses virtual prototyping to enable intelligent trade-offs between power and performance early in the design cycle Software Hardware Architecture Physical Implementation Silicon Process Power Management 2015 Synopsys, Inc. 2

3 SoC Power Analysis How does architecture affect energy consumption? Architecture Decisions (examples) HW/SW partitioning Best cache size and organization? How to achieve low latency without starvation? How to avoid page misses? Multicore CPU L 2 Multicore CPU L 2 DMA PCIe GMAC Cache Coherent Interconnect DDR Memory SRAM Memory SRAM Memory Power Management Decisions (examples) Power domain per core or entire CPU? Run fast and stop or DVFS? Turn off when idle? Timeout for moving to low power states? Accelerators 2015 Synopsys, Inc. 3

4 Problems with Spreadsheets Static calculations don t reflect multicore behavior Static Spreadsheets? Risk of over- / under-design Very large and complex Only average values for a complete use-case sequence Manual identification of worst-case scenarios Limited set of scenarios No dynamic interaction of system activity, architecture performance, and power management 2015 Synopsys, Inc. 4

5 Problems with Spreadsheets Static calculations don t reflect multicore behavior Static Spreadsheets? Risk of over- / under-design Under-design Performance issues Fix by increasing the clock rate? Schedule impact? (timing closure, verification issues) Energy consumption? (power issues) Over-design Power, Cost issues Fix with more expensive package? Re-spin? Cancel project? 2015 Synopsys, Inc. 5

6 Power Aware Architecture Design for Multicore SoCs Spec SoC Implementation Place & Route Fab Dynamic Multicore Simulation Early Analysis of Performance and Power Months sooner Months sooner Static estimates Validate performance Measure power Specification available RTL available Routed netlist & parasitics available 2015 Synopsys, Inc. 6

7 Virtual Prototype and Power Model Visible Events in Virtual Prototype Voltage/frequency Signal access Register/memory access TLM port access Events/counters/statistics Static and dynamic parameters Self-timed state transition Function calls trigger Power State Machine (overlay) Off uw/state mw/state Standby uw/state Transmit uw/state Receive uw/state Virtual Prototype Performance Model Performance and Power Analysis 2015 Synopsys, Inc. 7

8 What-If Power Analysis CPU load Freq. trace Power stats Power Management CPU Impact on load Performance Freq. trace Impact on Power Power stats 2015 Synopsys, Inc. 8

9 IEEE Standardization Goal: Interoperable IP Power Models Extend 1801 UPF for system level design Dedicated System Level Power Modeling sub-group System and power architecture, EDA and IP representation Targeting IEEE 1801 UPF 3.0 release in 2015 Visit Synopsys, Inc. 9

10 Power Aware Architecture Design for Multicore SoCs Dynamic Simulation and Analysis Quality Results Months Sooner Uses virtual prototyping to enable intelligent tradeoffs between power and performance early in the design cycle Non-intrusive overlay approach, leveraging existing IP power information Unified view of activity, performance, and power Aligned with emerging IEEE standards 2015 Synopsys, Inc. 10

11 Thank You

12 2015 Synopsys, Inc. 12