Design Techniques for Implementing an 800MHz ARM v5 Core for Foundry-Based SoC Integration. Faraday Technology Corp.

Transcription

1 Design Techniques for Implementing an 800MHz ARM v5 Core for Foundry-Based SoC Integration Faraday Technology Corp.

2 Table of Contents Faraday & FA626TE Overview Why We Need an 800MHz ARM v5 Core Why CPU Optimization is Different Design Techniques 5 System Level Considerations 6 Summary 2

3 Faraday: At a Glance Fabless ASIC and IP supplier Spun off from UMC in 1993 Strategic IP partnership with UMC UMC owns 20% of Faraday Focused fabless business model 2006 revenue: $171 million Listed in Taiwan Exchange since 1999 Today s Operation: 700 employees worldwide, 550+ in R&D HQ in Taiwan, branch offices in USA, Europe, Japan, and China 3

4 Faraday ARM s Valued Partner CPU Instruction Set Arch. Licensee ARMv4 and v5tej instruction set license Only few tier-one companies have such capability to license and develop ARM-Compliant cores. ARM SUDL Partner Single Usage ARM processor hard core sub-licensed ARM7TDMI, ARM922T, ARM946E Tool Distributor Exclusive tool distributor in Taiwan Tool-Kit (ADS, RVDS) Developing platform (Integrator..) ARM926EJ-S Core Licensee Well versed Synthesis skill, physical design and verification expertise w/ proprietary library. Smallest hard core & highest performance. 4

5 FA626TE Overview 32-bit RISC processor core with ARM v5te instruction set 8-stage pipeline, AXI / AHB interface 32KB I/32KB D caches ICE Interface Optional I/D scratch pads ARM tool chain support ICE Branch Target Buffer Coherence Hardware AXI / AHB I Cache ASIE I/F CPU Core I Scratch Pad D Scratch Pad D Cache Memory Management Unit Bus Interface Bus Interface Power Saving Write Buffer 5

6 Why We Need an 800MHz ARM v5 Core Application Integration Cost Applications need high performance : OLPC IP-STB Industrial PC High-Speed Network Infortainment Mobile Convergence Device SOHO NAS / Home NAS Thousands of softwares need to be computing : Algorithms and logic that are risky to build as hardwares Complex middlewares Sophisticated application softwares 800MHz CPU in UMC 90nm process : To reduce mask cost and design cycle contrast to 65nm High performance CPU in foundry provides ease-of-integration and cost saving 6

7 Integrate 800MHz CPU into PC SoC Faraday s PC SOC Plan FA626TE CPU 2D Engine DRAM DRAM DDRII Memory CTRL Display Engine DVI/LVDS Flash 1x SATA Security Engine Connectivity Video Engine Wireless LAN KB/Mouse/LPC 2x PCI Express x1 4 x USB2.0 WiMAX 3G/3.5G 7

8 Target Applications Low Cost PC/ Mobile Device (Web, Word/Excel Video, Education) Faraday SOC features -Integration -Low power -Low cost -WinCE/Linux Embedded (Thin Client Panel PC POS Digital Signage IPTV) 8

9 Why ARM Based SoC is Competitive Faraday SoC Major X86 Solution Trend 2007/E 2008,H2 CPU + MPU FC-2 2D + PC SoC Graphics NB + + SB SB Faraday ARM SoC X86 Solution Solution All-in-One Integrated Processor + SB CPU 800M~1GHz ~1GHz GPU 2D Integrated 2D/3D Integrated Video Engine Integrated Accelerator Only Power 2W 5W Price (CPU + CS) A Few Much 9 9

10 Why CPU Optimization is Different General embedded CPU optimization methods Micro Architecture Library & Memory Process Generation Micro-architecture Process Generation Library & Memory Pipeline Superscalar Multithread 64bit 65nm 45nm 32nm High speed cell library High speed memory 10

11 Why CPU Optimization is Different Faraday optimization methods Speed (MHz) 1, Circuits Pipeline Optimization Cycle Time (ns) 11

12 Faraday CPU Technology Technology Benefit Data-path TLB, reg file MHz, T2M Design Database Clock Gating Power De-skew MHz Over Driving MHz Circuit Implementation Testing Specific Cell Library Fast SRAM Sense-Amp DFF Power Island Structural Approach for Speed Binning MHz MHz MHz Power MHz 12

13 Register File Improvements In < 0.5um, RF is NOT difficult However, It creates congestions (32 x 32 DFF, muxes, multiple ports) Its performance determines forwarding path time budget Therefore, automated RF makes P&R easy, and eliminates routing congestion Improvements: 200 ps 13

14 Next Obvious Improvement is TLB FA626TE TLB needs fullassociativity But bit comparators is HUGE So we use the same methodology Result has same benefit as RG ~ 300 ps gain, instead of loss 14

15 Custom Design Process De-skew Step 1 I. Place the CPU block, figure out rough size Step 2 II. Rip out all cells and place clock trunk first Step 3 III. Place ALL DFF then, and make some rough grouping to ZERO out clock uncertainty. Step 4 IV. Place the rest of the cells 15

16 How to Do Circuit Implementation Higher Driving Capability Logic 1.2V Over Driving Enlarge cell to 11.5 grid Library Custom One-Hot Mux Memory 1.2V Over Driving Sense Amplifier based DFF 16

17 Structural Approach for Speed Binning Speed binning with delay test Advantages: Structural approach with Automated pattern generation. Issues need to be overcome: Decide critical path and correlate to true silicon longest paths Test condition different from actual system mode operation Good path selection to pick a set of representative paths is key to speed binning Need to do correlation between achieved speed with structural test patterns and system test 17

18 How to reach 1GHz FA626TE PMOS TT 900MHz 1.18% 1GHz 1.26% 1.36% FF 1.13% 800MHz SS NMOS Simulation result Speed binning at typical voltage result in 90nm for 18% - 36% performance Cost impact With three bins, there is an estimated additional 5% - 10% increase in die cost (to be confirmed) due to potential yield loss 18

19 System Diagram FA626TE processor Static controller L2 cache controller DDRII controller Others or application specific logic AMBA3 AXI Interconnect Bus AXI 2 AHB bridge AXI Interconnect DMA controller AMBA High Speed Bus - AHB AHB 2 APB bridge AHB controller Others or application specific logic AMBA2 Peripheral Bus - APB UART GPIO I2C/I2S SSI Others or application specific logic 19

20 System Level Considerations Need to consider the multiple in system clock 01.Clock Domain frequency design. Support synchronous mode Power Domain Core voltage (1.2V) is different from peripherals (1.0V) Need to consider gate delay when adding the level shift Need to add the regulator to support multi-voltage 03.Signal Domain Level shift to support signal conversion 20

21 Summary FA626TE Positioning Faraday Optimization Design Technology System Consideration 90nm TLB Optimization For the Changeful Algorithms and Various S/W Target Applications are OLPC, ULPC, IPC, IP-STB and Design Data Path Circuit Implementation Testing Register File Optimization De-Skew Methodology Specific Cell Library and Memory Clock Domain Power Domain Signal Domain Network Speed Binning 21

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