All Programmable: from Silicon to System

Transcription

1 All Programmable: from Silicon to System Ivo Bolsens, Senior Vice President & CTO Page 1

2 Moore s Law: The Technology Pipeline Page 2

3 Industry Debates Variability Page 3

4 Industry Debates on Cost Page 4

5 Nothing New: Power Challenge Multi-Core Source: Intel Page 5

6 Nothing New: Productivity Gap ESL Design Flow Source: SEMATECH Page 6 IP Re-Use

7 Nothing New: I/O Bandwidth Gap Multi-Gigabit SerDes Source: Xilinx, Inc. Page 7

8 Doubt is not an agreeable condition, but certainty is absurd. François-Marie Arouet de Voltaire, French Philosopher Photo Source: Wikipedia Page 8

9 Don t believe everything you read on the Internet. Abraham Lincoln, U.S. President Photo Source: Wikipedia Page 9

10 Extending and Leveraging Moore s Law Add Value : Programmable System Integration Programmability 3D Integration Collaborate Supply Chain Wider more Complexity Deeper earlier Engagement From System to Silicon Page 10

11 Value of Programmability: Configurability Partial Reconfiguration Time-multiplexing hardware Lower Power Page 11

12 Value of Programmability: I/O 28.05Gb/s 13.1Gb/s Quad B Ch 1 TX SFP+ Test Board Optical Quad A Ch 1 RX Quad A Ch 0/1/2/3 TX 12.5 Gb/s Quad B Ch 0/2/3 TX Backplane Quad B Ch 0/1/2/3 RX Quad A Ch 0/2/3 RX 6.6Gb/s Page 12

13 Value of Programmability: GOPS/Watt ARM CoreSight Multi-core & Trace Debug NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches ACP m s Interface AXI4 LITE interconnect s s s 512 KB L2 Cache Snoop Control Unit (SCU) m m m m AXI_DMA AXI_DMA Timers / Counters 256 KB On-Chip Memory s s General Interrupt Controller DMA Configuration AMBA Switches Accelerator Accelerator From 100 Watt to 2 Watt 10x Performance Acceleration Page 13

14 Future Challenge: HW + SW co-design OpenCL ARM Processor A9 C Compile / Debug A9 Commercial Software Ecosystem HW-SW Integration Video codec C-HLS Accelerator synth Encryption FPGA Packet Processing FFT Application-Specific Search Exploit Parallelism and Heterogeneity Page 14

15 3D Integration: Add Value Page 15

16 Value of 3D Integration: Bandwidth/Watt 100x 3D Interconnect BW / Watt 10x SerDes & Standard I/O 1x 10x 100x 1,000x Total Die-to-Die Connections 100x bandwidth/watt advantage over conventional methods Page 16

17 Value of 3D Integration: Cost/Gate Big Single Monolithic Die Multiple Small Die Slices Die Cost Greater capacity, faster yield ramp Page 17 Area

18 Value of 3D Integration: Heterogeneous ICs Logic Memory PLD Mixed functions Analog Memory Processor Mixed processes Page 18

19 Value of 3D Integration: Heterogeneous ICs Highest bandwidth FPGA with 2.78 Tb/s serial connectivity Electrically-isolated 28G transceivers for optimal signal integrity Homogeneous digital logic Different silicon processes 28G Transceivers 28G Transceivers Passive interposer Noise isolation 13G Transceivers Page 19

20 Value of 3D Integration: Lower Power Silicon Interposer with 28nm FPGA Slices 7 Series Static Power vs. Logic Cells at Tj=85C and Max Process 28 nm FPGA Slice nm FPGA Slice 28 nm FPGA Slice 28 nm FPGA Slice Max Static Power Virtex-7 Monolithic - Virtex-7 Multi-Slice 0.0 A B C D Very Leaky LCs/1000 Slow Fast Page 20

21 3D Integration: Challenges Ahead Improve Cost Wafer backside processing is complicated Device quality wafers used for interposers KGD methodologies still emerging Scalability Micro-bump scaling is limited Super-sized interposers. Improve TSV aspect ratio Design Support Multi-die analysis without Multi-mode Multi-corner explosion Thermal modeling based on vertical hotspots Page 21

22 3D Integration: Industry Call-to-Action Design Enablement Manufacturing Standards Models 3D Process Development Kit DFM rules for TSV, µ-bump Materials TSV, µ-bump Thermal budget Test Interoperability of Silicon Test HW Known-good-die method µ-bump probing Burn-in bare die Thin wafer handling Shipping methods Chip-to-chip interfaces Page 22

23 Supply Chain Collaboration: Early Engagement Stacked Silicon Interconnect Development Started 90nm Process Integration And Modular Development 90nm Test Vehicle Completed 65nm Test Vehicle Completed 28nm Test Vehicle Completed Design Tools Available Heterogeneous Stacked Silicon Interconnect Technology Initial Reliability Assessment Design Enablement and Supply Chain Validation Process Qualification Design Validation Today World s First 3D Stacked Silicon Interconnect Device 3D Integration Page 23

24 Supply Chain Collaboration: Early Engagement Technology path finder Integration and basic devices Basic elements: RAM, RF, Std Cell, etc. Circuit blocks, process-design interactions, pilot prep More circuit blocks, & later products 28nm starts TV0 TV1 TV2 TV3 TV4 TV nm Process Technology Page 24

25 Supply Chain Collaboration: Product Ramp Up FAB Advanced InIn-Line Inspection FPGA Wafer Sort Root Cause Analysis Yield Improvement Continuous, early feedback loop for initial ramping Enables accelerated learning days vs. months Page 25

26 Supply Chain Collaboration: Mutual Benefit FPGA architecture drives yield & quality improvements The FPGA is a powerful yield learning vehicle with multiple layers of programmable features Defect Reduction: quick to detect defects If you can t find it, you can t fix it Process Control: powerful to measure variations If you can t measure it, you can t improve it Page 26

27 Supply Chain Test FAB Bump DB Assy Outside In-house Bin Mark FG PP Page 27

28 Today s Supply Chain R&D Consortia EDA, Equipment Suppliers FAB Sort µ Bump DB bins Die Sep Top die attach Test Outside In-house Bin Mark Std efuse1 efuse2 FG Chip-on-Die 3rd party die Top side proc. Bot side proc. Bump Interposer I-poser attach Chip-on-Wafer PP Pkg assy Bump Top side proc. Interposer 3rd party die Bot side proc. Die stack Wider and Deeper Page 28

29 From Silicon to System System Company FablessVendor Applications SW System Architecture Product Features Product IP/HW/SW How to monetize SW? Power, performance cost, integration DFM How to ramp yield faster? Supplier Package Wafer Who controls 3D supply chain? Page 29

30 Conclusions Moore s Law: - From mostly cost reduction to more value-based innovation System figure of merit defines value Xilinx programmable system integration - Programmability - 3D integration Supply chain partnerships to enable - Efficiency - Standardization - Innovation Page 30

31 What Xilinx Makes Possible: ALL PROGRAMMABLE ALL Programmable Electronic Systems ALL Programmable Technologies ALL Programmable Devices Page 31

32 Follow Xilinx facebook.com/xilinxinc twitter.com/#!/xilinxinc youtube.com/xilinxinc Page 32