Department of Electrical and Computer Engineering, University of Rochester, Computer Studies Building,

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1 ,, Computer Studies Building, BOX , Rochester, New York (phone) kose Research Interests and Vision Research interests: Design methodologies for high performance digital and mixed-signal high performance integrated circuits; On-chip power/clock network design and analysis; On-chip voltage regulation; 3-D integration; Noise issues in on-chip interconnection networks. Research vision: Develop novel circuits and architectures that will facilitate the integration of emerging technologies in the circuit design process of power efficient heterogeneous nano- and bio-electronic systems. Education Doctor of Philosophy in Electrical and Computer Engineering March expected May 2012 Advisor: Professor Eby G. Friedman Dissertation: High Performance Power Delivery in Nanoscale Integrated Circuits Master of Science in Electrical and Computer Engineering September March 2008 Bilkent University Bachelor of Science in Electrical and Electronics Engineering September May 2006 Work Experience Research Assistant, High Performance Integrated Circuit Design Laboratory Co-design of clock and power distribution networks Design of on-chip voltage regulators Designed, fabricated, and tested an ultra-small hybrid on-chip voltage regulator Algorithms for efficient power grid analysis Interconnect related noise issues; analysis and mitigation techniques September Current Freescale Semiconductor Tempe, AZ Graduate Intern, Microwave and Mixed-Signal Laboratory May August 2010 Analyzed the EM emissions generated by an integrated circuit Developed design methodologies for reducing the EM emissions Eastman Kodak Company Graduate Intern, CMOS Image Sensors R&D Laboratory May June 2009 Designed and fabricated a test chip for a hybrid voltage regulator Intel Corporation Santa Clara, CA Graduate Intern, Central Technology and Special Circuits Team May August

2 Worked on optimizing the reference clock distribution network Investigated and optimized the performance of level shifters used witin the clock distribution network Intel Corporation Santa Clara, CA Graduate Intern, Central Technology and Special Circuits Team May August 2007 Responsible for functional verification of the de-skew machine and all related circuit block in the un-core clock distribution network Identified a number of bugs in the de-skew machine in the early phase of the design Performed reliability verification analysis of the clock and cache distribution networks The Scientific and Technological Research Council of Turkey Part-Time Engineer, VLSI Design Center March June 2006 Worked on efficient low-power on-chip integration of image processing algorithms Nanomagnetics Instruments Technical Intern June August 2005 Worked on PLL card for a scanning hall probe microscope Teaching Experience Teaching Assistant in Electrical and Computer Engineering Department September May 2008 VLSI Design Methodologies Circuits and Signals Introduction to Signals and Circuits Bilkent University Teaching Assistant September May 2006 Analog Electronics Microprocessors Awards Turkiye Is Bankasi Golden Youth Award for outstanding success in University Entrance Exam 12 th over 1.5 million candidates, Turkey, 2001 Full scholarship and stipend awarded by Bilkent University,, Awarded with Abroad Undergraduate Education Fellowship by Turkish Government, Turkey,

3 Publications Book B1. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Kose, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edition, Springer, Journals J1. S. Kose and E. G. Friedman, Effective Resistance of a Two Layer Mesh, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 11, pp , November J2. S. Kose, E. Salman, and E. G. Friedman, Shielding Methodologies in the Presence of Power/Ground Noise, IEEE Transactions on Very Large Scale Integration (VLSI) Circuits, Vol. 19, No. 8, pp , August J3. S. Kose and E. G. Friedman, Fast Algorithms for Localized Power Grid Analysis, Integration, the VLSI Journal (in press). J4. S. Kose, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, Active Filter Based Hybrid On-Chip DC-DC Converters for Point-of-Load Voltage Regulation, IEEE Transactions on Very Large Scale Integration (VLSI) Circuits (under review). J5. S. Kose, R. M. Secareanu, O. L. Hartin, and E. G. Friedman, Current Profile Estimation to Determine the Electromagnetic Emissions for a Broad Frequency Range, IEEE Transactions on Very Large Scale Integration (VLSI) Circuits (in preparation). J6. I. Savidis, S. Kose, and E. G. Friedman, Power Noise in TSV-based 3-D Integrated Circuits, IEEE Journal of Solid-State Circuits (in preparation). Conferences C1. S. Kose, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, An Area Efficient On-Chip Hybrid Voltage Regulator, Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March C2. S. Kose and E. G. Friedman, Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality, Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp , June C3. S. Kose and E. G. Friedman, Distributed Power Network Co-Design with On-Chip Power Supplies and Decoupling Capacitors, Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), June C4. I. Savidis, S. Kose, and E. G. Friedman, Power Grid Noise in TSV-Based 3-D Integrated Systems, Government Microcircuit Applications and Critical Technology Conference (GOMACHTech), pp , March C5. S. Kose and E. G. Friedman, Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors, Proceedings of the IEEE International SoC Conference, pp , September C6. S. Kose and E. G. Friedman, An Area Efficient Fully Monolithic Hybrid Voltage Regulator Proceedings of the IEEE International Symposium on Circuits and Systems, pp , May/June

4 C7. S. Kose and E. G. Friedman, Fast Algorithms for Power Grid Analysis Based on Effective Resistance, Proceedings of the IEEE International Symposium on Circuits and Systems, pp , May/June C8. S. Kose and E. G. Friedman, On-Chip Point-of-Load Voltage Regulator for Distributed Power Supplies, Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp , May C9. S. Kose, E. Salman, and E. G. Friedman, Shielding Methodologies in the Presence of Power/Ground Noise, Proceedings of the IEEE International Symposium on Circuits and Systems, pp , May C10. S. Kose, E. Salman, Z. Ignjatovic, and E. G. Friedman, Pseudo-Random Clocking to Enhance Signal Integrity, Proceedings of the IEEE International SoC Conference, pp , September Workshop Presentations W1. I. Vaisband, S. Kose, I. Savidis, and E. G. Friedman, On-Chip Power Delivery, University Technology Showcase, Rochester, New York, April 6, Invited Talks EMMA: A Methodology to Model Current Activity of a Digital Block to Determine Emission Level for a Broad Frequency Range, RF, Analog, and Sensor Group, Freescale Semiconductor, Tempe, Arizona, August Simultaneous Co-Design of Clock and Power Distribution Networks, Central Technology and Special Circuits Team, Intel Corporation, Santa Clara, California, March Un-Core Clock Distribution of Nehalem-Ex Processor and the De-Skew Machine Operation Principles, Central Technology and Special Circuits Team, Intel Corporation, Santa Clara, California, August Grants Contributed significantly to writing several proposals including proposals for the following awards: Qualcomm Award: Distributed On-Chip Power Delivery in Low Power Multi-Core Communication Circuits, , $80,000. (PI: E. G. Friedman) NSF Award: Distributed On-Chip Power Delivery for Heteregenous Integrated Circuits, , $1,200,000. (PI: E. G. Friedman; Co-PI: E. Ipek) in submission Professional Service External reviewer Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Circuits (TVLSI), IEEE Transactions Circuits and Systems-II (TCAS-II), IEEE Transactions Computer-Aided Design (TCAD), IEEE Electron Device Letters (EDL), ASP Journal of Low Power Electronics (JOLPE), Analog Integrated 4

5 Circuits and Signal Processing, Integration, the VLSI Journal, IET Circuits, Devices & Systems, Microelectronics Journal. Conferences: International Symposium on Quality Electronic Design (ISQED), Design, Automation and Test in Europa (DATE), International Conference on Circuits and Systems (ISCAS), International Conference on Computer Design (ICCD), System-on-Chip Conference (SOCC), Asia Pacific Conference on Circuits and Systems (APCCAS), International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), Asia Symposium on Quality Electronic Design (ASQED), International Symposium on Networks-on-Chip (NOCS), Great Lakes Symposium on VLSI (GLSVLSI), International Conference on Very Large Scale Integration (VLSI-SOC). 5

6 References Eby G. Friedman, Distinguished Professor Rochester, New York Phone: (585) Simon Tam, Senior Principle Engineer Intel Corporation Santa Clara, California Phone: (415) Engin Ipek, Assistant Professor Department of Computer Science Rochester, New York Phone: (585) Zeljko Ignjatovic, Associate Professor Rochester, New York Phone: (585) Baris Taskin, Associate Professor Drexel University Philadelphia, Pennsylvania Phone: (215)