New ARMv8-R technology for real-time control in safetyrelated

Transcription

1 New ARMv8-R technology for real-time control in safetyrelated applications James Scobie Product manager ARM Technical Symposium China: Automotive, Industrial & Functional Safety October 31 st 2016 November 4 th 2016

2 Today s presentation Increasing system complexity New ARM Cortex-R52 processor Functional safety support Software separation Real-time execution Where Cortex-R52 fits 2

3 Increasing complexity in functional safety markets Automotive Cleaner engines Industrial Factory automation Healthcare Robotic surgery Autonomous driving Smart robots Advanced medical mobility 3

4 Autonomous systems share a common foundation Autonomous system Sense Perceive Decide Actuate Gather environment information from sensors Filter, interpret and understand sensor data Safely choose actions Initiate actions 4

5 Complementary processor solutions High-performance compute Application processors Fast real-time control Real-time processors Coherent multicore ARM big.little technology Extended safety ISO ASIL D Performance Efficiency Determinism Safety Security 5

6 Collaborative robots Sense Perceive Decide Actuate Flexible operation Higher levels of autonomy Functional safety demand Real-time control for decision and actuation Collaborative autonomy Autonomous flexible operation Autonomous drones 6

7 Advanced driver assistance systems (ADAS) Sense Perceive Decide Actuate Rising-system complexity Higher levels of autonomy Functional safety demand Real-time control for decision and actuation Lane detection Lane keeping Highway pilot City pilot Adoption time 7

8 Cortex-R52: the most advanced processor for safety Simplifying functional safety. Providing enhanced-safety features and safety support ARM s highest performance real-time processor for safety applications Enhanced software reliability and simplified software consolidation with real-time, deterministic virtualization 8

9 Cortex-R52: first implementation of new ARMv8-R architecture Cortex-R5 Real-time performance with functional safety Cortex-R52 Most advanced processor for functional safety Functional safety Cortex-R7 High-performance 4G modem and storage Cortex-R8 Highestperformance 5G modem and storage Storage and modem Legend: ARMv7-R ARMv8-R 9

10 Protection against Functional safety controls risks of hazards Safety application Safety application Random errors Systematic faults Run-time errors Design errors Software errors Patient-controlled drug delivery Braking system Product safety features Processes 10

11 Functional safety for ARM Cortex processors Cortex-R52 Cortex-M3/M4 Cortex-M0+ Exception handling MPU Cortex-A ARMv8-A Cache parity / ECC Exception handling MMU RAS features (v8.2-a) Cortex-M33 Cortex-M23 Dual core lockstep ECC interface Exception handling MPU Stack limit check Cortex-M7 TCM ECC interface MBIST interface Dual core lockstep Cache ECC Exception handling MPU Cortex-R5 Bus ECC Error management TCM ECC MBIST interface Dual core lockstep Cache ECC Exception handling MPU Virtualization Bus protection SW test library System Error Bus ECC Error management TCM ECC MBIST interface Dual core lockstep Cache ECC Exception handling Two-stage MPU 11 Standard systematic capability Standard safety package: Safety manual, FMEA report, development interface report Extended systematic capability Extended safety package: Safety manual, FMEA report, development interface report 3 rd party functional safety assessment report availability depending on processor

12 Cortex-R52 extended functional safety support Random errors Systematic faults Fault management New privilege level Bus-interconnect protection Dual-core lockstep Self-test library Error management System event interrupt ECC-protected memory and busses Two-stage MPU Processes Developed within robust requirements tracing and validation framework Safety manual Failure modes and effects analysis Development interface report Providing support for SIL 3 / IEC ASIL D / ISO

13 Growth in software complexity Safety-critical function Safety function Applications providers SoC Mixed software With different criticality From multiple sources Resulting in Complex integration Large, complex safety certification SoC SoC 13

14 Reducing software complexity Software separation Simplified integration of complex software from multiple sources Reduced effort for certification Real-time execution maintained Safety-critical function Safety function Applications providers SoC 14

15 Cortex-R52 simplifies real-time software separation The only processor with real-time deterministic virtualization ARMv8-R architecture introduces an additional exception level Create sandboxes protected from other software Safe task A Safe task B Task C Task D Monitor (or hypervisor) manages software separation and simplifies isolation of tasks RTOS Monitor Real-time switch rapidly between tasks and sandboxes Cortex-R52 15

16 Enabling consolidation onto fewer platforms 150 different subsystems in a car >100 million lines of code Complete operating systems and tasks virtualized Safe task A Safe task B Task C Task D RTOS RTOS Hypervisor Cortex-R52 16

17 Relative iso-frequency performance Cortex-R52 delivers best-in-class performance x 1.30x 1.25x Up to 35% performance uplift AutoMark* DMIPS CoreMark Cortex-R5 Cortex-R52 14x faster context switch 2x faster interrupt entry Compared to Cortex-R5 17 * Green Hills compiler

18 Advanced features and capabilities Deterministic microarchitecture In-order execution Superscalar pipeline with extensive dual issuing Integer and floating-point calculations Advanced SIMD instructions Optional ARM NEON Double-precision floating point Cycle-redundancy check instructions Scalability From 1 to 4 cores Up to 4 cores in lockstep 18

19 Built for real-time determinism Deterministic memory Scalable tightly coupled memory for fast access Flexible data or instruction allocation Extensibility Rich set of interface ports Dedicated low-latency ports Wide Flash interface port Fastest interrupt entry 2x faster than Cortex-R5 Interrupt controller integrated within cluster Rapid responsiveness 14x faster context switch than Cortex-R5 Hard real-time determinism 19

20 Cortex-R52 provides real-time performance Real-time control systems Dual-core lockstep system Sense Decide Actuate SoC Multiple homogeneous processors Execute both safety and application software Sensors Cortex-R52 Cortex-R52 Cortex-R52 Cortex-R52 CoreLink interconnect Ideal for applications such as Industrial control Powertrain Chassis Lockstep processor 20

21 Creating a safety island with Cortex-R52 Autonomous system Sense Perceive Decide Actuate Combined as a safety island with application processors Sensors SoC Cortex-A Cortex-A Cortex-R52 Cortex-A Cortex-A CoreLink interconnect Partitioned for safety and determinism vs throughput Ideal for applications such as Robotics ADAS Lockstep processor 21

22 I Cortex-R52 Functional safety Virtualization Real-time performance CPU Delay Delay CPU Delay Memory Delay 64-bits ECC bits 64-bits ECC bits 64-bits ECC bits 64-bits ECC bits 64-bits ECC bits Checkers 64-bits ECC bits 64-bits ECC bits 64-bits ECC bits ECC detect & correct Processor Data (and Instructions) Address & Control ECC generate ECC chk/crrct Parity generate Parity check ECC Data ECC Data Parity Addr/Ctrl Parity Addr/Ctrl ECC chk/crrct ECC generate Parity check Parity generate Interconnect logic ECC generate ECC chk/crrct Parity generate Parity check Memory system Safe Task A RTOS Safe Task B Task C Monitor / Hypervisor RTOS Task D CPU 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits 32-bits ECC bits ECC generate ECC detect & correct RMW if <32b D Cortex-R52 Comprehensive features for fault detection and control Developed for safety Application consolidation Systematic fault protection High-performance execution Fast deterministic response Flexible memory system 22

23 The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2016 ARM Limited