4/11/17. Agenda. Princeton University Computer Science 217: Introduction to Programming Systems. Goals of this Lecture. Storage Management.
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1 //7 Prnceton Unversty Computer Scence 7: Introducton to Programmng Systems Goals of ths Lecture Storage Management Help you learn about: Localty and cachng Typcal storage herarchy Vrtual memory How the hardware and OS gve applcaton pgms the lluson of a large, contguous, prvate address space Vrtual memory s one of the most mportant concepts n system programmng Agenda Localty and cachng Typcal storage herarchy Vrtual memory Storage Devce speed vs. sze Facts: CPU needs subnanosecond access to memory (else t can t run nstructons fast enough) Fast memores (subnanosecond) are small ( bytes), Bg memores (ggabytes) are slow ( nanoseconds) Huge memores (terabytes) are very slow (mllseconds) Goal: Need many ggabytes of memory, but wth fast (subnanosecond) average access tme Soluton: localty allows cachng Most programs exhbt good localty A program that exhbts good localty wll beneft from proper cachng Localty Two nds of localty Temporal localty If a program references tem X now, t probably wll reference X agan soon Spatal localty If a program references tem X now, t probably wll reference tems n storage nearby X soon Most programs exhbt good temporal and spatal localty Localty Example Localty example sum = ; for ( = ; < n; ++) sum += a[]; Typcal code (good localty) Temporal localty Data: Whenever the CPU accesses sum, t accesses sum agan shortly thereafter Instructons: Whenever the CPU executes sum += a[], t executes sum += a[] agan shortly thereafter Spatal localty Data: Whenever the CPU accesses a[], t accesses a[+] shortly thereafter Instructons: Whenever the CPU executes sum += a[], t executes ++ shortly thereafter
2 //7 Cachng Cache Fast access, small capacty storage devce Acts as a stagng area for a subset of the tems n a slow access, large capacty storage devce Good localty + proper cachng Most storage accesses can be satsfed by cache Overall storage performance mproved Cachng n a Storage Herarchy Level : Level +: 9 Blocs coped between levels Smaller, faster devce at level caches a subset of the blocs from level + Larger, slower devce at level + s parttoned nto blocs 7 8 Cache Hts and Msses Cache Evcton Polces Cache ht E.g., request for bloc Access bloc at level Fast! Cache mss E.g., request for bloc 8 Evct some bloc from level to level + Load bloc 8 from level + to level Access bloc 8 at level Slow! Level : 8 9 Level +: Level s a cache for level Best evcton polcy: clarvoyant polcy Always evct a bloc that s never accessed agan, or Always evct the bloc accessed the furthest n the future Impossble n the general case Worst evcton polcy Always evct the bloc that wll be accessed next! Causes thrashng Impossble n the general case! Cachng goal: Maxmze cache hts Mnmze cache msses 9 Cache Evcton Polces Localty/Cachng Example: Matrx Mult Reasonable evcton polcy: LRU polcy Evct the least recently used (LRU) bloc Wth the assumpton that t wll not be used agan (soon) Good for straght-lne code (can be) bad for loops Expensve to mplement Often smpler approxmatons are used See Wpeda Page replacement algorthm topc Matrx multplcaton Matrx = two-dmensonal array Multply n-by-n matrces A and B Store product n matrx C Performance depends upon Effectve use of cachng (as mplemented by system) Good localty (as mplemented by you)
3 //7 Localty/Cachng Example: Matrx Mult Two-dmensonal arrays are stored n ether row-maor or column-maor order row-maor col-maor a[][] 8 a[][] 8 a a[][] 9 a[][] 8 9 a[][] a[][] a[][] a[][] 9 a[][] a[][] Localty/Cachng Example: Matrx Mult for (=; <n; ++) for (=; <n; ++) for (=; <n; ++) c[][] += a[][] * b[][]; a[][] a[][] a[][] a[][] C uses row-maor order Access n row-maor order good spatal localty Access n column-maor order poor spatal localty a[][] a[][] a[][] a[][] Reasonable cache effects Good localty for A Bad localty for B Good localty for C a b c Localty/Cachng Example: Matrx Mult Localty/Cachng Example: Matrx Mult for (=; <n; ++) for (=; <n; ++) for (=; <n; ++) c[][] += a[][] * b[][]; for (=; <n; ++) for (=; <n; ++) for (=; <n; ++) c[][] += a[][] * b[][]; Poor cache effects Bad localty for A Bad localty for B Bad localty for C a b c Good cache effects Good localty for A Good localty for B Good localty for C a b c Agenda Typcal Storage Herarchy Localty and cachng Typcal storage herarchy Vrtual memory Smaller faster storage devces regsters L cache Level cache Level cache CPU regsters hold words retreved from L/L/L cache L/L/L cache holds cache lnes retreved from man memory man memory (RAM) Man m em or y holds ds blocs r etr eved fr om local dss Larger slower storage devces local secondary storage (local dss, SSDs) Local dss hold fles retreved from dss on remote networ servers 7 remote secondary storage (dstrbuted fle systems, Web servers) 8
4 //7 Typcal Storage Herarchy Typcal Storage Herarchy Regsters Latency: cycles Capacty: 8- regsters 8 general purpose regsters n IA-; n typcal RISC machne (ARM, MIPS, RISC-V) L/L/L Cache Latency: to cycles Capacty: KB to MB Man memory (RAM) Latency: ~ cycles tmes slower than regsters Capacty: MB to GB Local secondary storage: ds drves Latency: ~, cycles tmes slower than man mem Lmted by nature of ds Must move heads and wat for data to rotate under heads Faster when accessng many bytes n a row Capacty: GB to TB 9 Typcal Storage Herarchy Asde: Persstence Remote secondary storage Latency: ~,, cycles tmes slower than ds Lmted by networ bandwdth Capacty: essentally unlmted Another dmenson: persstence Do data persst n the absence of power? Lower levels of storage herarchy store data persstently Remote secondary storage Local secondary storage Hgher levels of storage herarchy do not store data persstently Man memory (RAM) L/L/L cache Regsters Asde: Persstence Admrable goal: Move persstence upward n herarchy Sold state (flash) drves Use sold state technology (as does man memory) Persstent, as s ds Vable replacement for ds as local secondary storage Storage Herarchy & Cachng Issues Issue: Bloc sze? Slow data transfer between levels and + use large bloc szes at level (do data transfer less often) Fast data transfer between levels and + use small bloc szes at level (reduce rs of cache mss) Lower n pyramd slower data transfer larger bloc szes Devce Regster L/L/L cache lne Man memory page bloc transfer bloc Bloc Sze 8 bytes bytes KB (9 bytes) KB (9 bytes) KB (9 bytes) to MB (788 bytes)
5 //7 Storage Herarchy & Cachng Issues Issue: Who manages the cache? Devce Regsters (cache of L/L/L cache and man memory) L/L/L cache (cache of man memory) Man memory (cache of local sec storage) Local secondary storage (cache of remote sec storage) Managed by: Compler, usng complex codeanalyss technques Assembly lang programmer Hardware, usng smple algorthms Hardware and OS, usng vrtual memory wth complex algorthms (snce accessng ds s expensve) End user, by decdng whch fles to download Agenda Localty and cachng Typcal storage herarchy Vrtual memory Man Memory: Illuson Man Memory: Realty Process Process Process VM ory Process VM unmapped Memory for Process Memory for Process FFFFFFFF unmapped FFFFFFFF FFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFF Each process sees man memory as Huge: = EB ( exabytes) of memory Unform: contguous memory locatons from to - 7 Memory s dvded nto pages At any tme some pages are n physcal memory, some on ds OS and hardware swap pages between physcal memory and ds Multple processes share physcal memory 8 Vrtual & Physcal Addresses Vrtual & Physcal Addresses (cont.) How do OS and hardware mplement vrtual memory? Answer (part ) Dstngush between vrtual addresses and physcal addresses Vrtual address vrtual page num offset Identfes a locaton n a partcular process s vrtual memory Independent of sze of physcal memory Independent of other concurrent processes Conssts of vrtual page number & offset Used by applcaton programs Physcal address physcal page num offset Identfes a locaton n physcal memory Conssts of physcal page number & offset Known only to OS and hardware Note: Offset s same n vrtual addr and correspondng physcal addr 9
6 //7 CourseLab Vrtual & Physcal Addresses CourseLab Vrtual & Physcal Addresses vrtual addr physcal addr vrtual page num offset bts bts physcal page num offset vrtual addr physcal addr vrtual page num offset bts bts physcal page num bts offset bts On CourseLab: Each offset s bts Each page conssts of bytes Each vrtual page number conssts of bts There are vrtual pages Each vrtual address conssts of bts There are bytes of vrtual memory (per process) On CourseLab: Each offset s bts Each page conssts of bytes Each physcal page number conssts of bts There are physcal pages Each physcal address conssts of 7 bts There are 7 (8G) bytes of physcal memory (per computer) s s (cont.) How do OS and hardware mplement vrtual memory? Answer (part ) Mantan a page table for each process for Process Vrtual Page Num Physcal Page Num or Addr Physcal page (unmapped) Spot X on ds Physcal page 8 Page table maps each n-use vrtual page to: A physcal page, or A spot (trac & sector) on ds ory Example Process Process Process accesses mem at vrtual addr 8 8 = B = Vrtual page num = ; offset = X Y X Y ory Example (cont.) Process Process Hardware consults page table Hardware notes that vrtual page maps to phys page Page ht! X Y X Y
7 //7 ory Example (cont.) Process Process Hardware forms physcal addr Physcal page num = ; offset = = B = 98 Hardware fetches/stores data from/to phys addr 98 X Y X Y 7 ory Example Process Process Process accesses mem at vrtual addr 8 8 = B = Vrtual page num = ; offset = 8 X Y X Y 8 ory Example (cont.) Process Process X Y X Hardware consults page table Hardware notes that vrtual page maps to spot X on ds Page mss! Hardware generates page fault Y 9 ory Example (cont.) Process Process Y X X OS gans control of CPU OS swaps vrtual pages and Ths taes a long whle (ds latency), run another process for the tme beng; then eventually... OS updates page table accordngly Control returns to process Process re-executes same nstructon Y ory Example (cont.) Process Process Process accesses mem at vrtual addr 8 8 = B = Vrtual page num = ; offset = 8 Y X X Y ory Example (cont.) Process Process Y X X Hardware consults page table Hardware notes that vrtual page maps to phys page Page ht! Y 7
8 //7 ory Example (cont.) Process Process Hardware forms physcal addr Physcal page num = ; offset = 8 = B = 9 Hardware fetches/stores data from/to phys addr 9 Y X X Y ory Example Process Process Process accesses mem at vrtual addr = B = Vrtual page num = ; offset = 9 Y X X Y ory Example (cont.) Process Process Y X Hardware consults page table Hardware notes that vrtual page s unmapped Page mss! Hardware generates segmentaton fault (See Sgnals lecture for remander!) X Y Storng s Where are the page tables themselves stored? Answer In man memory What happens f a page table s swapped out to ds???!!! Answer OS s responsble for swappng Specal logc n OS pns page tables to physcal memory So they never are swapped out to ds Storng s (cont.) Doesn t that mean that each logcal memory access requres two physcal memory accesses one to access the page table, and one to access the desred datum? Answer Yes! Isn t that neffcent? Answer Not really Storng s (cont.) Note Page tables are accessed frequently Lely to be cached n L/L/L cache Note X8- archtecture provdes specal-purpose hardware support for vrtual memory 7 8 8
9 //7 Translaton Looasde Buffer Addtonal Benefts of ory Translaton looasde buffer (TLB) Small cache on CPU Each TLB entry conssts of a page table entry Hardware frst consults TLB Ht no need to consult page table n L/L/L cache or memory Mss swap relevant entry from page table n L/L/L cache or memory nto TLB; try agan See Bryant & O Hallaron boo for detals Cachng agan!!! Vrtual memory concept facltates/enables many other OS features; examples Context swtchng (as descrbed last lecture) Illuson: To context swtch from process X to process Y, OS must save contents of regsters and memory for process X, restore contents of regsters and memory for process Y Realty: To context swtch from process X to process Y, OS must save contents of regsters and vrtual memory for process X, restore contents of regsters and vrtual memory for process Y Implementaton: To context swtch from process X to process Y, OS must save contents of regsters and page table for process X, restore contents of regsters and page table for process Y ponter to the ponter to the 9 Addtonal Benefts of ory Addtonal Benefts of ory Memory protecton among processes Process s page table references only physcal memory pages that the process currently owns Impossble for one process to accdentally/malcously memory used by another process affect physcal Memory protecton wthn processes Permsson bts n page-table entres ndcate whether page s readonly, etc. Allows CPU to prohbt Wrtng to RODATA & TEXT sectons Access to protected (OS owned) vrtual memory Lnng Same memory layout for each process E.g., TEXT secton always starts at vrtual addr x E.g., STACK always grows from vrtual addr 8 - to lower addresses Lner s ndependent of physcal locaton of code Code and data sharng User processes can share some code and data E.g., sngle physcal copy of stdo lbrary code (e.g. prntf) Mapped nto the vrtual address space of each process Addtonal Benefts of ory Dynamc memory allocaton User processes can request addtonal memory from the heap E.g., usng malloc() to allocate, and free() to deallocate OS allocates contguous vrtual memory pages and scatters them anywhere n physcal memory Addtonal Benefts of ory Creatng new processes Easy for parent process to for a new chld process Intally: mae new PCB contanng copy of parent page table Incrementally: change chld page table entres as requred See Process Management lecture for detals for() system-level functon Overwrtng one program wth another Easy for a process to replace ts program wth another program Intally: set page table entres to pont to program pages that already exst on ds! Incrementally: swap pages nto memory as requred See Process Management lecture for detals execvp() system-level functon 9
10 //7 Measurng Memory Usage On CourseLab computers: $ ps l F UID PID ID PRI NI VSZ RSS WCHAN STAT TTY TIME COMMAND sgnal TN pts/ : emacs nw wat SNs pts/ : -bash RN+ pts/ : ps l VSZ (vrtual memory sze): vrtual memory usage RSS (resdent set sze): physcal memory usage (both measured n lobytes) Summary Localty and cachng Spatal & temporal localty Good localty cachng s effectve Typcal storage herarchy Regsters, L/L/L cache, man memory, local secondary storage (esp. ds), remote secondary storage Vrtual memory Illuson vs. realty Implementaton Vrtual addresses, page tables, translaton looasde buffer (TLB) Addtonal benefts (many!) Vrtual memory concept permeates the desgn of operatng systems and computer hardware
Storage Management 1
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