Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK)

Transcription

1 Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK) Tsung-Ching Jim Huang, PhD Sr. Research Scientist, Hewlett Packard Labs MEPTEC2018

2 Outline Introduction Modeling and design needs for flexible hybrid electronics (FHE) FHE uses cases for internet of things (IoT) and healthcare Process design kit (PDK) for flexible hybrid Electronics FHE-PDK: the 1 st PDK dedicated to FHE; free/open to NextFlex members Overview of FHE-PDK: a superset of PDKs for FHE design-manufacture Phase I for electrical designs; phase II includes Multiphysics/package designs Models for printed interconnects, resistors, capacitors, and transistors Models for printed inductors, antennas and transmission lines (TL) under developments FHE design verifications and printed layout parasitics extraction Conclusion 2

3 Model and Design for Flexible Hybrid Electronics -- Integrated Thinned Silicon Chips and Printed Components Flexible Display Printed Interconnect Flexible Solar Cell Micro- Processor Printed Passives (R/C) Printed Antenna Source: NextFlex RF Transceiver Printed Transmission Lines (TL) 3

4 Flexible Hybrid Electronics Uses Cases for IoT and Healthcare HPE/Stanford/UCSB Pseudo-CMOS chip Disposable CNT ID-Tag Google Contact Lenses Wearable Glucose Sensor We aim to bring intelligent IoT infrastructure for smart everything (infrastructure, manufacturing, healthcare, logistics, energy, and so on). It is made possible by More-than-Moore integration of thinned silicon chips and printed components such as sensors, antennas, and passives. 4

5 Model and Design for Flexible Hybrid Electronics with FHE-PDK -- Integrated Thinned Silicon Chips and Printed Components Technical Areas Model What we have today 1.Chip model 2.IBIS package model What is still missing (FHE-PDK project goals) 1. Printed components (R/L/C/TL/Antenna/Transistor) 2. Thinned silicon chip model Design 2D electrical design, design verification 3D geometry input, design rules Simulation SPICE/Register-transfer level/gate-level Multiphysics (electrical-thermal-mechanical) IBIS Package Model Source: EDN Printed resistors Printed capacitors Printed TL 5

6 NextFlex is Cooperated by DoD and FlexTech Alliance since 2015 NextFlex Mission: Usher in the era of electronics on everything and advance efficiency of our world FHE-PDK: 18-month contract ( ) between HPE and NextFlex to build world 1 st PDK for FHE 6

7 FHE-PDK to Enable FHE Design-Manufacture Open Ecosystem PDK is the missing piece for FHE to complete the designmanufacture loop; royaltyfree and open-source to all NextFlex members 7

8 FHE-PDK: A Superset of PDKs for Design-Manufacture Interaction Each PDK* (ex. A-E) includes models, design rules, technology files; multiple PDK libraries FHE Design Geometry and Specification Inputs by Users (ex. HPE, Boeing etc) Board/package design Multiphysics design Electrical design Design-for-manufacture specs Flex Board/Package Design Tools Multiphysics Design Tools IC Design Tools IC Verification Tools Flex board/package stack-up & parasitics models Multiphysics models Electrical models Design Rules PDK Library A (model, design rules, tech files) PDK Library B (model, design rules, tech files) PDK Library C (model, design rules, tech files) Flex Fabricator A (ex. Stanford) PDK_A PDK_B PDK_C PDK_D PDK_E Flex Fabricator B (ex. NextFlex) CMOS Fabricator C (ex. tsmc) Packaging House D (ex. Amkor) Assembly House E (ex. Flex) FHE-PDK Phase-I FHE-PDK Phase-II *NDA is required to obtain PDK from fabricators 8

9 Parasitic Models for Printed Interconnects and Traces - Examples of calibrating printed capacitor values with parasitics 9

10 Layout Parasitic Extraction for Post-Layout SPICE Simulations 10

11 Carbon-Nanotube (CNT) Resistor Array (864 samples shown) (W= 40 µm, L= 2 to 100 µm as shown in the plots) 11

12 Parallel-Plate Capacitor Array (431 samples shown) (D= 10 and 25 nm, W= 45 to 10,000 µm as shown in the table) 12

13 CNT-Transistor Model Validation (with 52 Fabricated CNT-TFTs) Compact Model Schematic Current Model Based on previous two observations, a compact model for CNT-TFT is presented here. Good match between measurements and model further validate our analysis I SD (A) Transfer Curve V S =0V, V D =-0.5V V GS Measure Model Measure Model V GS I SD (A)

14 Design Rule Checking for Printed Active and Passive Circuits 14

15 Layout versus Schematics Checking for Printed Circuits 15

16 Technology File Generation for Design Rule Checker 16

17 Parameterized Cell (P-Cell) for Printed Resistors 17

18 Summary and Future Outlook FHE is emerging for IoT, smart infrastrures, logistics and so on US FHE-MII (NextFlex) established in 2015 to promote FHE design-manufacture HPE is leading the efforts of building 1 st PDK dedicated to FHE design needs Process design kit for flexible hybrid electronics (FHE-PDK) Spice/verilog models for printed active and passive components Design rules checking and interconnect parasitics extraction for printed circuits Integrated environment for printed circuit and silicon chip co-development Able to take multiple PDKs from flex/chip fabricators as well as packaging houses 18

19 Back Up Slides 19

20 IoT Market Growth by Market Segments during x 20

21 IoT Market Growth from HW to Application/Services

22 Intelligent IoT Infrastructure via Billions of Connected IoT Nodes Enabling data analytics at IIoT nodes and edge computers Node #1 Node #8 Node #2 Node #7 AI Cloud /HPC Unit Node #3 Source: ARM Node #6 Node #5 Node #4 Supervise Control Update IIoT nodes and edges are capable of sensing and performing applications and analytics locally where the data is generated for actionable insights. IIoT node/edge only updates key information to the cloud with to enhance data security, reduce latency, and save power. 22

23 1.77 inch Real-Time Monitoring and Root Cause Analysis for Smart Pump Pressure, temperature, and vibration sensor 8.32 inch 23

24 FHE for Data Acquisition/ Pre-Processing Virtually Anywhere Today Tomorrow Applications Source: Uniqarta Source: NI crio FHE enables limitless possibilities for intimate sensing, data acquisition, and computing for intelligent IoT nodes 24

25 FHE for IoT Hardware Design from 2D to 3D Stretchable Surface Apple Watch 3 Printed Circuit Board Packaged IC Passives Antenna CNT logic chip Ultra-thin CMOS die Asset Tracking Tag 2.45GHz Antenna(HPE) CNT Resistor Array (HPE- Stanford) 25

26 Comparison of Switching Elements The Transistors Transistor Technology Process Temperature Process Technology Crystalline Si-MOSFET Amorphous Si TFT Metal-Oxide TFT Organic TFT Carbon Nanotube TFT < 150 < 100 Room Temp. Lithography Lithography Lithography Ink-Jet/ Shadow Mask Lithography/ Shadow Mask Feature Size 7 nm 8 μm 5 μm 50 μm 2 μm Substrate Wafer Glass/plastics Glass/plastics Wafer/plastics Wafer/plastics Device Type Complementary N-type N-type Complementary Complementary Supply Voltage 0.8 V 20V 10V 20V 3V Mobility (cm 2 /Vs) /0.5 (N/P) 25 Cost / Area Very High Medium Medium Low Very Low Lifetime Very Good Good Good N:Poor/ P: Good N:Poor/ P:Good MOSFET: Metal-oxide-semiconductor field-effect transistor; TFT: Thin-film transistor 26