Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface
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1 Thierry Berdah, Yafit Snir Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface
2 Agenda Typical Verification Challenges of MIPI CSI-2 SM designs IP, Sub System and System Level Verification Simulation verification methodology for MIPI CSI-2 SM spec compliancy Acceleration Methodology Overview Concepts for building MIPI CSI-2 SM acceleration-ready environment MIPI CSI-2 SM IP Level: From simulation to acceleration 2018 MIPI Alliance, Inc. 2
3 MIPI CSI-2 adoption Widely adopted serial high-speed protocols Implemented in complex systems, for a variety of applications in different markets: Mobile Video Games Automotive Multimedia Virtual reality, augmented reality and others 2018 MIPI Alliance, Inc. 3
4 MIPI Interfaces usage example in Complex SOCs Arm CPU Subsystem Customer s Application Specific Components Software A15 A15 L2 cache A7 A7 L2 cache 3D Graphics Core DSP A/V Application Accelerators AES Cache Coherent Fabric SoC Interconnect Further complicated by hardware/ software interactions LPDDR3 PHY 3.0 PHY USB PHY PCIe Gen 2,3 PHY High speed, wired interface peripherals Ethernet PHY SATA SAS SD MIPI UFS Other Memory Storage & Memory MIPI CSI-2 SM MIPI DigRF MIPI D-PHY MIPI DSI SM MIPI M-PHY MIPI SoundWire I2C Low-speed MIPI LLI peripheral JTAG MIPI subsystem UniPro MIPI high speed peripheral interfaces, and other MIPI Alliance, Inc. 4
5 MIPI CSI-2 SM Verification Challenges Reach system verification coverage goals prior to code freeze MIPI CSI-2 SM spec compliancy based on design and system configuration Time to market: Requires parallel development of hardware and software design, early in development cycle Validating software and hardware integration Create and validate real world scenarios in a pre-silicon environment 2018 MIPI Alliance, Inc. 5
6 Design Verification Flow IP IP IP Sub Sys Sub Sys SOC IP Verification Subsystem System Simulation Acceleration Accelerated Basic MIPI CSI-2 SM Testsuite Full Verification Testsuite 2018 MIPI Alliance, Inc. 6
7 IP-Level Verification IP vplan IP IP IP Verification s Basic Testsuite Full Testsuite Compliance s checkers Debug DUT issues s Coverage Model Coverage closure Create Tests Integrate (s) 2018 MIPI Alliance, Inc. 7
8 Sub-System/SoC Level Verification Sub Sys SOC Sub Sys Subsystem System s s As As Testsuite Create Tests Protocol and system debug tools Debug DUT Issues Coverage Emulation Coverage Coverage Integrate (s) or A(s) 2018 MIPI Alliance, Inc. 8
9 Verification methodology for Spec compliancy Spec verification is based on two aspects: 1. MIPI CSI-2 SM spec compliance Protocol checking based on MIPI CSI-2 SM spec Coverage aligned to the design configuration Complete Testsuite to cover MIPI CSI-2 SM DUT 2. System behavioral correctness Integrity checking based on system definition UVM Config Monitor checking coverage CSI-2 SM Agent Sequencer (sequence driver) Driver (BFM) DUT 2018 MIPI Alliance, Inc. 9
10 Verification methodology for Spec compliancy User needs full visibility into and controllability over on Configuration, traffic injection, protocol checking and functional coverage Testbench (User Layer) Integrity checking (Scoreboard) Configuration Transaction Callback Compliance Testsuite Protocol checking 2018 MIPI Alliance, Inc. 10
11 Verification methodology for Spec compliancy 1. Test Suite Ready to use, spec driven tests Optimized combination of Directed and Constrained-random sequences Reaching 100% of the Verification Plan Filtered per DUT configuration Early & Fast verification 2. Functional Coverage Native verification language database Reachable and tested Filtered per user configuration Complete coverage of your configuration Full Verification 3. Verification Plan Protocol-meaningful verification objectives Linked to coverage database Filtered to match DUT specific configuration Able to integrate with simulation tools Easy to understand correlation of coverage results to protocol specification 2018 MIPI Alliance, Inc. 11
12 Verification methodology for Spec compliancy TestSuite vplan, Coverage and TestSuite based on DUT config Transaction Tests Physical Layer Tests Pipe Tests Configuration Tests Link Layer Tests User feeds the DUT s specific Configuration Monitor UI BFM configured To DUT Configuration File Specification Of My Architecture DUT specific info is created Native Coverage DUT 2018 MIPI Alliance, Inc. 12
13 How to create the MIPI CSI-2 SM Verification Plan? 2018 MIPI Alliance, Inc. 13
14 Development Flow and Tools Map IP IP IP IP Verification Simulation SubSys SubSys Subsystem Accelerated SOC System TEXT Gradient shapes Acceleration to A Migration 2018 MIPI Alliance, Inc. 14
15 Why Acceleration? Software Arm CPU Subsystem A15 A15 A7 A7 L2 cache L2 cache Cache Coherent Fabric 3D Graphics Core Customer s Application Specific Components DSP A/V Application Accelerators AES SoC Interconnect LPDDR3 PHY USB PHY 2.0 PHY PCIe Gen 2,3 PHY Ethernet PHY High speed, wired interface peripherals SATA SAS SD MIPI UFS Other Memory Storage & Memory MIPI CSI-2 SM MIPI DigRF MIPI D-PHY MIPI DSI SM MIPI M-PHY MIPI SoundWire I2C MIPI LLI Low-speed peripheral JTAG MIPI subsystem UniPro MIPI high speed peripheral interfaces, and other. Complex SoCs, comprised of tens of millions of logic gates, will impede software simulators, even when running on the fastest servers MIPI Alliance, Inc. 15
16 Overview of hardware assisted verification Emulator assisted verification Simulation Acceleration Virtual Emulation In-Circuit Emulation FPGA Prototyping 2018 MIPI Alliance, Inc. 16
17 Simulation Acceleration & Accelerated Transaction Based Acceleration Workstation Communication Channel Palladium Z1 Testbench Seq Drv Mon TBA TBA B F M Design Under Test Workstation Accelerated (A) Emulator Signal Transaction Based Based Acceleration Acceleration Bit-by-bit Reduces communication signal level exchange channel between overhead testbench from signal and based DUTto Performance transaction based bottleneck can be the communication Leverages fast hardware channel for testbench DUT time execution 2018 MIPI Alliance, Inc. 17
18 Virtual emulation & Virtual Device Workstation Communication Channel Palladium Z1 Virtual Device Model P R O X Y TBA TBA B F M Design Under Test Workstation Virtual Device Emulator Signal Virtual Based emulation Acceleration Bit-by-bit Enables testing signal the level design exchange with realworld traffic testbench and DUT Performance Leverages fast bottleneck hardware can for DUT be the between communication execution channel or testbench time 2018 MIPI Alliance, Inc. 18
19 MIPI CSI-2 SM Virtual Device SOC Design Enables visualization of the HW/SW operation of the video/image processing subsystem in real time SW stack/drivers MIPI CSI-2 SM Virtual Device Image files GPU Image processor Frame buffer MIPI CSI-2 SM Host Controller MIPI CSI-2 SM A BFM SW Proxy MIPI CSI-2 SM Virtual Device Model Model Logic Emulator Workstation 2018 MIPI Alliance, Inc. 19
20 MIPI CSI-2 SM Emulation/Prototyping with real sensor SOC Design Enables connection of real sensors to emulated SOC designs for live video and closed loop testing SW stack/drivers GPU Image processor Frame buffer MIPI CSI-2 SM Host Controller MIPI CSI-2 SM Real Sensor Emulator MIPI CSI-2 SM Rate Adapter 2018 MIPI Alliance, Inc. 20
21 Concepts for building an acceleration-ready environment Use consistent API for s/as Use Dual-Top structure for the verification environment The Hardware top will include the DUT, Interfaces, clocks generation, etc. The software top will include the SW Verification Environment. Use event based delays instead of cycle/time based delays whenever possible. Pre define simulation and acceleration subset of shared sequences Simulator User API Shared A/ API Core Shared A/ Interface DUT Consistent SW API Consistent HW API Simulator User API Shared A/ API Accelerated Core Shared A/ Interface DUT Emulator 2018 MIPI Alliance, Inc. 21
22 MIPI CSI-2 SM IP Level: From simulation to acceleration Simulation stage Software Top (Simulator) User User Sequences User Sequences Sequences Hardware Top (Simulator) Pixel Custom UVC MIPI CSI-2 SM A/ Shared API APB A/ Shared API MIPI CSI-2 SM Active Agent Core MIPI CSI-2 SM A PPI IF MIPI CSI- 2 SM RX DIP APB IF APB A APB APB Active ActiveAgent Agent Core MIPI CSI-2 SM Passive Agent CSI2 Passive MIPI CSI-2 SM Clocks gen APB APB Passive APB Passive Agent 2018 MIPI Alliance, Inc. 22
23 MIPI CSI-2 SM IP Level: From simulation to acceleration Step #1 Disabling passive agents used at IP level stage Software Top (Simulator) User User Sequences User Sequences Sequences Hardware Top (Simulator) Pixel Custom UVC MIPI CSI-2 SM A/ Shared API APB A/ Shared API MIPI CSI-2 SM Active Agent Core MIPI CSI-2 SM A PPI IF MIPI CSI- 2 SM RX DIP APB IF APB A APB APB Active ActiveAgent Agent Core Clocks gen 2018 MIPI Alliance, Inc. 23
24 MIPI CSI-2 SM IP Level: From simulation to acceleration Step #2 Migrating to Accelerated s Software Top (Simulator) User User Sequences User Sequences Sequences Hardware Top (Simulator) Pixel Custom UVC CSI2 A/ Shared API Accelerated Accelerated APB A/ Shared API MIPI CSI-2 SM Accelerated Active Agent Core MIPI CSI-2 SM A PPI IF MIPI CSI- 2 SM RX DIP APB IF APB A APB Accelerated APB Active Active Agent Core Agent Clocks gen 2018 MIPI Alliance, Inc. 24
25 MIPI CSI-2 SM IP Level: From simulation to acceleration Step #3 Choosing the subset of sequences required for acceleration Software Top (Simulator) Identifying A/ Shared sequences User User Sequences User Sequences Sequences Hardware Top (Simulator) Pixel Custom UVC CSI2 A/ Shared API Accelerated Accelerated APB A/ Shared API MIPI CSI-2 SM Accelerated Active Agent Core MIPI CSI-2 SM A PPI IF MIPI CSI- 2 SM RX DIP APB IF APB A APB Accelerated APB Active Active Agent Core Agent Clocks gen 2018 MIPI Alliance, Inc. 25
26 MIPI CSI-2 SM IP Level: From simulation to acceleration Step #4 Migrating to acceleration flow Software Top (Simulator) User User Sequences User Sequences Sequences Hardware Top (Simulator) Pixel Custom UVC Design run time Accelerated! CSI2 A/ Shared API Accelerated Accelerated APB A/ Shared API MIPI CSI-2 SM Accelerated Active Agent Core MIPI CSI-2 SM A PPI IF MIPI CSI- 2 SM RX DIP APB IF APB A APB Accelerated APB Active Active Agent Core Agent Clocks gen 2018 MIPI Alliance, Inc. 26
27 Summary: Advantages of using acceleration Enables orders-of-magnitude gains in throughput over Simulation Enables re using selected parts of your simulation verification environment Enables advanced technologies with virtual emulation, like: Hybrid operation for optimal partition of the design between HW and SW to achieve maximum speedup Connection to Virtual Devices, Virtual machines, etc. Enables OS-level benchmarks and driver bring-up 2018 MIPI Alliance, Inc. 27
28 ADDITIONAL RESOURCES MIPI Camera WG URL: MIPI CSI-2 SM Spec URL: Cadence Verification IP URL: Cadence Accelerated URL: MIPI Alliance, Inc. 28
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