Latches SEU en techno IBM 130nm pour SLHC/ATLAS. CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France

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1 Latches SEU en techno IBM 130nm pour SLHC/ATLAS CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France

2 Outline Introduction Description of the DICE latch Different implemented layouts for the DICE latch Measurement and comparison of implemented latches Proposed implementation for the pixel configuration block Conclusion 2/11

3 Introduction hardened by design (HBD) approaches are used to reduce the effect of single bit upsets. Dual Interlocked Cell (DICE) latches have redundant storage nodes dual node and theoretically restores the original state when an upset occurs in one node. The upset may appear if the charge collected in two nodes exceed the critical value test circuits using the130 nm CMOS process designed in order to study the effect of layout techniques on the tolerance of the DICE latch to single event upsets. Irradiation tests were carried out using IRRAD3 beam line of the Proton Synchrotron (PS) facility at CERN. The test beam provides a beam of 24 GeV protons Proposed structure for : Pixel configuration block Global configuration block 3/11

4 Dice Latch description inb The DICE latch is based on the conventional cross coupled inverter latch structure If we assume a positive upset pulse on the node X2 load outb MP3 is blocked (ON -> OFF) avoiding the propagation of this perturbation to the node X3 MP1 MP2 MP3 MP4 X1 X2 X3 X MN1 MN2 MN3 MN4 load out For a single node, the critical charge is very high (~1 pc) If 2 sensitive nodes of the cell storing the same logic state (X1-X3) or (X2-X4) are corrupted due to the effect of a single particle impact, the immunity is lost and the Dice latch is upset. in The critical charge becomes low (~40 fc) when a charge from upset is collected by a sensitive node pair 4/11

5 Sensitive areas inb For out =1 Sensitive pair node load MP1 MP2 MP3 MP4 OFF ON OFF ON X1 1 X2 0 X3 1 X4 0 outb out X1=X3=1 and X2=X4=0 Sensitive area corresponds to the OFF transistor drain area Sensitive area has to be minimized ON OFF ON OFF MN1 MN2 MN3 MN4 Spatial separation for the drain of MN1-MN3, MN2-MN4 load Contacted guard ring and nwell separation for pmos MP1-MP3, MP2-MP4 in 5/11

6 Test Set up Control room irradiation area LabWindows software PCIMCIA acquisition board TTL -LVDS LVDS signals LVDS-TTL Serial link A Current supply control ~20 meters error_in parity_in TRL error parity TRL error parity TRL TRL error_out parity_out Readback Load serin D Q D Q D Q ck DFF ck DFF ck DFF ck DFF D Q serout clk Reset TRL : Triple redundant latch DFF : Standard Flip Flop 231 cells 6/11

7 Layouts implemented in the chip SEU1 FEI3_DICE latch (latch 1) Latch type area 1->0 Cross section (cm²/bit) Latch 1 54 µm² Latch Area = 54 µm² Latch 5 48 µm² Improved DICE latch (latch 5) Measurements made in 2007 for the chip SEU1 Latch Area = 48 µm² 7/11

8 Layouts implemented in the chip SEU2 Different layout versions were implemented in the SEU2 chip Latch 5: pmos in same nwell, enclosed and separated nmos with guard ring (pmos separation: 8µm, nmos separation: 2.4µm) Same schematic but different layout Latch type area Cross section cm²/bit 1->0 0->1 1->0 and 0->1 Latch 5.2: pmos in isolated nwell, enclosed nmos with guard ring (pmos separation: 4µm, nmos separation: 8µm) Latch 5 48 µm² (1.5 ± 0.1) (2.2 ± 0.3) (5.9 ± 0.5) Latch µm² (3.4 ± 0.6) (4.2 ± 0.4) (3.6 ± 0.5) Latch µm² (3.0 ± 0.6) (3.3 ± 0.3)10-16 (2.4 ± 0.5) Measurements made in 2008 for the chip SEU2 Latch 5.3: same structure like latch 5.2 with interleaved layout Pmos separation: 5.4µm, nmos separation: 9µm) 8/11

9 «SEULATCH_wGate» schematic Old schematic New schematic A modified schematic is proposed : Remove the «latchclear» signal We add a readback option for all latches to improve tests The latch clear operation can be done by loading pattern FEI4-Proto DICE latch 36µm² 9/11

10 proposed layout Configbloc_wGate 22µm A1 C2 50µm 30µm B1 C1 D2 A2 D1 B2 150µm 37µm A1 C2 E1 F1 G2 H2 B1 D2 G1 I2 C1 A2 H1 E2 D1 B2 I1 F2 A1 DICE latch A2 Interleaved structure In order to improve the SEU tolerance we are using interleaved layout for each latch in the pixel configuration block 1 elementary cell 10/11

11 Future Finalize proposal layout in FEI4-P2 for several columns Fit SEU tolerant latch in the pixel dedicated area Finalize interconnections to realize an interleaved structure Fit SEU tolerant latch for global configuration block Using triple redundant latch Prepare future radiations tests: work with a higher frequency (40MHz) 11/11