MAX 10. Memory Modules
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1 MAX 10 Memory Modules
2 Three types of on-chip memory FF based memory embedded in the LEs Most efficient for very small memories Compiler driven Embedded SRAM block 8K bits parity bits (9216b) MAX 10-M50 has 182 blocks 1,456Kb + parity = 1,677,312b total User Flash User Programmable 5,888Kb Configuration - 10,752Kb 2 tj
3 FF based memory embedded in the LEs Register File Static N bits wide M bits deep Synchronous (using DFF) Asynchronous (using latches) Inefficient for all but the smallest memories 3 tj
4 RegFile.vhdl created 7/19/17 -- tj rev Register File for memory size notes Inputs: rstb, clk, reg_write, reg_read_addr -- reg_write_addr, reg_write_data -- Outputs: reg_read_data library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity RegFile is generic( REG_NUM: natural := 4; REG_DATA_WIDTH: natural := 8 ); port (clk : in std_logic; rstb : in std_logic; end entity; On-Chip Memory FF based memory embedded in the LEs reg_write: in std_logic; reg_read_addr: in std_logic_vector((integer(ceil(log2(real(reg_num))))-1) downto 0); reg_write_addr: in std_logic_vector((integer(ceil(log2(real(reg_num))))-1) downto 0); reg_write_data: in std_logic_vector(reg_data_width downto 0); reg_read_data: out std_logic_vector(reg_data_width downto 0) ); architecture behavioral of RegFile is Register File -- type reg_type is array (0 to (REG_NuM - 1)) of std_logic_vector(reg_data_width downto 0); signal reg_file: reg_type; begin Register File Write -- register_write_process: process(clk, rstb) begin if(rstb = '0') then reg_file <= ((others=> (others=>'0'))); elsif(rising_edge(clk) and (reg_write = '1')) then reg_file(to_integer(unsigned(reg_write_addr))) <= reg_write_data; end if; end process; Output Logic -- reg_read_data <= reg_file(to_integer(unsigned(reg_read_addr))); end architecture; 4 tj
5 FF based memory embedded in the LEs 8b x 4 9b x 1024 Equivalent to one M9K block 5 tj
6 Functional configurations Single-port Simple dual-port True dual-port (bidirectional dual-port) Shift register ROM FIFO buffers Memory Based Multiplier 6 tj
7 M4K Fixed Memory Blocks Data width (word) configurations Parity used as memory Packed Mode Single Port configuration Each M9K block can be broken into 2 independent memories Each memory must be less than ½ the full block size 18 bit word size maximum Each memory has only single clock support 7 tj
8 Byte Enable SRAM only Multi-byte words can be masked Src: MAX 10 Device Handbook 8 tj
9 Byte Enable Src: MAX 10 Device Handbook 9 tj
10 Address Clock Enable Holds the previous address input until enabled Clock gate Implemented as a Stall Src: MAX 10 Device Handbook 10 tj
11 Address Clock Enable - read Src: MAX 10 Device Handbook 11 tj
12 Address Clock Enable - write X X Src: MAX 10 Device Handbook 12 tj
13 Clock Modes Src: MAX 10 Device Handbook 13 tj
14 Additional Control Signals Clock Enable Enables the clock If no clock is enabled no memory activity Asynchronous Clear Clears the output data register if present No clear for the input data register Read/Write Several variations depending on mode 14 tj
15 Data flow-through All inputs are registered Outputs can be synchronous or asynchronous Read-during-write-mode Single port, true Dual Port Write data flows through to the output 15 tj
16 Read during Write Write complete 16 tj
17 Mixed Port Configurations 17 Src: MAX 10 Device Handbook tj
18 ROM SRAM with memory pre-loaded from a MIF file Single Port Read only Single Clock In/Out Clock 18 tj
19 ROM SRAM with memory pre-loaded from a MIF file Dual Port Read only Single Clock In/Out Clock A/B Clock 19 tj
20 Single Port RAM Single Clock Dual Clock Src: MAX 10 Device Handbook 20 tj
21 Single Port RAM - write Write addr captured Async data flow through with delay Sync data flow through with 1 clk + td delay Src: Cyclone II Device Handbook 21 tj
22 Single Port RAM - read Read addr captured Async read with delay Sync data read with 1 clk + td delay Src: Cyclone II Device Handbook 22 tj
23 Simple Dual Port RAM Separate read and write addresses Simultaneous read and write Data in and out ports do not have to have matching widths 23 tj
24 Simple Dual Port RAM Single Clock R/W Clock In/Out Clock 24 tj
25 Simple Dual Port RAM Src: Cyclone II Device Handbook 25 tj
26 True Dual Port RAM Supports 2 reads, 2 writes, Read/Write Multiple clock options Data in and out ports do not have to have matching widths 26 tj
27 True Dual Port RAM Multiple R/W Ports Single Clock R/W Clock In/Out Clock 27 tj
28 M4K Fixed Memory Blocks True Dual Port RAM Src: Cyclone II Device Handbook 28 tj
29 Multi-tap Shift RAM Multiple M4K blocks can be cascaded Src: Cyclone II Device Handbook 29 tj
30 FIFO Separate read and write clocks available Separate read and write data widths available Empty and Full signals 30 tj
31 Memory Based Multiplier 31 tj
32 Memory Based Multiplier 32 tj
33 Memory Based Multiplier 33 tj
34 User Flash Memory Nonvolatile available for User Flash in some configurations 34 tj
35 User Flash Memory Parallel Mode Operation 35 tj
36 User Flash Memory Parallel Mode Operation - WRITE 36 tj
37 User Flash Memory Parallel Mode Operation - READ 37 tj
38 User Flash Memory Parallel Mode Operation BURST READ 38 tj
39 User Flash Memory Serial Mode Operation 39 tj
40 User Flash Memory Serial Mode Operation - WRITE 40 tj
41 User Flash Memory Serial Mode Operation - READ 41 tj
42 User Flash Memory Serial Mode Operation BURST READ 42 tj
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