Introduction to SRAM. Jasur Hanbaba

Transcription

1 Introduction to SRAM Jasur Hanbaba

2 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Non-volatile Memory Manufacturing Flow

3 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM

4 Memory Types: Volatile: Random Access Memory (RAM): SRAM "static" DRAM "dynamic" Non-volatile: Read Only Memory (ROM): Mask ROM "mask programmable" EPROM "electrically programmable" EEPROM "erasable electrically programmable" FLASH memory - similar to EEPROM with programmer integrated on chip

5 Why is memory design important Memory arrays often account for the majority of transistors in modern microprocessor designs. So it is critical to have a memory design that is efficient in terms of area and fast. SRAM (static random access memory) is the most widely used in processor design. Simplicity: internal feedback loop that retain its value as long as power is applied. Compatible with standard CMOS processes. Faster than DRAM.

6 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline word bit bit_b 13: SRAM Slide 6

7 1-bit cell of the SRAM

8 bit bit_b SRAM Read word N2 P1 P2 N4 Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip word A A_b N1 bit N3 bit_b A_b 0.5 A time (ps)

9 bit bit_b SRAM Write word N2 P1 P2 N4 Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 >> P bit_b A A_b N1 A N3 A_b 0.5 word time (ps)

10 SRAM Column Example Read Write B itlin e C o n d itio n in g Bitline Conditioning φ 2 w o rd _ q 1 bit_v1f M o re C e lls S R A M C e ll bit_b_v1f word_q1 More Cells φ 2 φ 1 φ 2 H o u t_ b _ v 1 r H o u t_ v 1 r write_q1 bit_v1f SRAM Cell bit_b_v1f w o rd _ q 1 b it_ v 1 f o u t_ v 1 r data_s1

11 SRAM Layout Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary

12 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A1 A0 word0 word1 word2 word3 A1 A word word0 word1 word2 word3 1/2 A0 A word 8

13 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15

14 Predecoding Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort A3 A2 A1 A0 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15

15 Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing

16 Bitline Conditioning Precharge bitlines high before reads bit φ bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers φ bit bit_b

17 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline t pd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce V)

18 Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 N2 P2 sense bit_b N3

19 Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b

20 Column Multiplexing 2 n words of 2 m bits each. If n >> m, fold by 2 k into fewer rows of more columns Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers Good regularity easy to design Very high density if good cells are used wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits column circuitry

21 Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A1 A1 A2 A2 Y to sense amps and write circuits Y

22 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y

23 SRAM Layout

24 Non-volatile Memory Used to hold fixed code (ex. BIOS), tables of data (ex. FSM next state/output logic), slowly changing values that persist over power off (date/time) Mask ROM Used with logic circuits for tables etc. Contents fixed at IC fab time (truly write once!) EPROM (erasable programmable) & FLASH requires special IC process (floating gate technology) writing is slower than RAM. EPROM uses special programming system to provide special voltages and timing. reading can be made fairly fast. rewriting is very slow. erasure is first required, EPROM - UV light exposure, EEPROM electrically erasable

25 Manufacturing Flow Wafer fab E-Test Sort Assembly Burn-in Class Structural Functional PPV Customer Front end Back end The front end = wafer fab, E-test, E and sort. E-test E and sort are also called wafer test. In assembly, wafers are cut into dice and the dice are assembled into packages. The back end = assembly, burn-in, class test and PPV.