The Art of Parallel Processing

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1 The Art of Parallel Processing Ahmad Siavashi April 2017

2 The Software Crisis As long as there were no machines, programming was no problem at all; when we had a few weak computers, programming became a mild problem, and now we have gigantic computers, programming has become an equally gigantic problem." 1972, Turing Award Lecture Edsger W. Dijkstra The Art of Parallel Processing - Siavashi 2

3 1 st Software Crisis (~ 60s & 70s) Assembly Language Programming Complex Programs C, FORTRAN, HW dependent Low Abstraction The Art of Parallel Processing - Siavashi 3

4 2 nd Software Crisis (~ 80s & 90s) Handling Multi-million lines of code Maintainability C++, C#, Java, Libraries, Design Patterns, Software Engineering Methods, Tools Composability The Art of Parallel Processing - Siavashi 4

5 Until Yesterday Programmers were oblivious to processors High level languages abstracted away the system E.g., Java byte code is machine independent Performance was left to Moore s Law The Art of Parallel Processing - Siavashi 5

6 Moore s Law Gordon Moore 1965 Circuit complexity doubles every year 1975 (revised) Circuit complexity doubles every 1.5 years The Art of Parallel Processing - Siavashi 6

7 The Free Lunch Instead of improving the software, wait for the hardware to improve E.g., doubling the speed of a program may take 2 years If technology improves 50%/year In 2 years, = 2.25 So the investment is wrong! Unless it also employs new technology The Art of Parallel Processing - Siavashi 7

8 But Today, The Free Lunch Is Over! There were limiting forces (Brick wall) Power wall Memory wall Instruction-Level Parallelism (ILP) wall The Art of Parallel Processing - Siavashi 8

9 Limit #1: Power Wall Power dynamic C. V 2 dd. f C = Capacitance V dd = Supply voltage f = Frequency Power static = I leakage. V dd The Art of Parallel Processing - Siavashi 9

10 Limit #2: Memory Wall Each memory access requires hundreds of CPU cycles Source: Sun World Wide Analyst Conference Feb. 25, 2003 The Art of Parallel Processing - Siavashi 10

11 Limit #3: ILP Wall Since 1985, all processors use pipelining to overlap the execution of instructions. This potential overlap among instructions is called Instruction-Level Parallelism, since the instructions can be evaluated in parallel. Ordinary programs are written and executed sequentially. IPL allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in which instructions are executed. How much ILP exists in programs is very application specific. The Art of Parallel Processing - Siavashi 11

12 Limit #3: ILP Wall (Cont d) Example: A loop that adds two 1000-element arrays for (int i = 0; i < 1000; i++) { C[i] = A[i] + B[i]; } Every iteration of the loop can overlap with any other iteration. Such techniques works by unrolling the loop either statically by the compiler or dynamically by the hardware. The Art of Parallel Processing - Siavashi 12

13 Limit #3: ILP Wall (Cont d) Superscalar designs were the state of the art Multiple instruction issue Dynamic scheduling Speculative execution etc. You may have heard of these, but you haven t needed to know about them to write software! Unfortunately, these sources have been used up. The Art of Parallel Processing - Siavashi 13

14 Revolution is Happening Now Chip density is continuing increase ~2x every 2 years Clock speed is not Number of processor cores may double instead There is little or no hidden parallelism (ILP) to be found Parallelism must be exposed to and managed by software The Art of Parallel Processing - Siavashi 14

15 Evolution of Microprocessors Ref: Intel processors: Shekhar Borkar, Andrew A. Chien, The Future of Microprocessors. Communications of the ACM, Vol. 54 No. 5, Pages / Oracle M7: Timothy Prickett Morgan Oracle Cranks Up The Cores To 32 With Sparc M7 Chip, Enterprise Tech - Systems Edition, August 13, The Art of Parallel Processing - Siavashi 15

16 If you were plowing a field, which would you rather use? Two strong oxen or 1024 chickens? - Seymour Cray - The Art of Parallel Processing - Siavashi 16

17 Pictorial Depiction of Amdahl s Law Unaffected, fraction: (1- F) Affected fraction: F Unchanged Unaffected, fraction: (1- F) F/S F = The fraction enhanced S = The speedup of the enhanced fraction Overall speedup = Execution time without enhancement Execution time with enhancement = 1 1 F + F S The Art of Parallel Processing - Siavashi 17

18 Amdahl s Law Overall speedup = 1 1 F + F S F = The fraction enhanced S = The speedup of the enhanced fraction Example. Overall speed up if we make 80% of a program run 20% faster. Gene Myron Amdahl F = 0.8 S = 1.2 The Art of Parallel Processing - Siavashi = 1.153

19 Amdahl s Law for Multicores Overall speedup = 1 1 F + F N F = The parallelable fraction N = Number of cores Hence, running a program on a dual core doesn t mean getting two times the performance. if F 1 F or F > 1 F + overhead then speedup > 0 Gene Myron Amdahl The Art of Parallel Processing - Siavashi 19

20 Myths and Realities 2 x 3GHz better than 6GHz Wrong 6GHz is better for single-threaded apps 6GHz may be better for multi-threaded apps due to the existing overheads (discussed latter) So, Why a dual core processor may run the same app faster? OS would run on another core, dedicating an idle core to the app The Art of Parallel Processing - Siavashi 20

21 3 rd Software Crisis (Present) Sequential Solution? performance is left behind by Moore s law Concurrency is the next major revolution in how we write software To No support perfect solution/implementation new features yet To There support is little larger or no datasets hidden parallelism (ILP) to be found Needed continuous and reasonable performance improvements Parallelism must be exposed to and managed by software Needed improvements while sustaining portability and maintainability The vast majority without of programmers unduly increasing today don t complexity grok concurrency, faced by the programmer just as the vast majority of programmers 15 years ago didn t yet grok objects. critical to keep-up with the current rate of evolution in software The Art of Parallel Processing - Siavashi 21

22 Concurrency Vs Parallelism The Art of Parallel Processing - Siavashi 22

23 Classes of Parallelism and Parallel Architectures Data Parallelism Task Parallelism The Art of Parallel Processing - Siavashi 23

24 Race Condition // Shared variable int sum = 0; // t threads running the code below for (int i = 0; i < N; i++) sum++; Where output is dependent on the sequence of accessing a shared resource The Art of Parallel Processing - Siavashi 24

25 Principles of Parallel Programming Finding enough parallelism (Amdahl s law) Granularity Locality Load balance Coordination and synchronization Performance modeling All of these things makes parallel programming even harder than sequential programming. The Art of Parallel Processing - Siavashi 25

26 Flynn s Classification The Art of Parallel Processing - Siavashi 26

27 SISD Single Instruction, Single Data Uniprocessors Implicit Parallelism Pipelining Hyperthreading Speculative execution Dynamic scheduling Scoreboard algorithm Tomasulo s algorithm Etc. The Art of Parallel Processing - Siavashi 27

28 Intel Pentium-4 Hyperthreading The Art of Parallel Processing - Siavashi 28

29 MIMD Multiple Instructions, Multiple Data A type of parallel system Every processor may be executing a different instruction stream working with a different data stream The Art of Parallel Processing - Siavashi 29

30 Parallel Computer Memory Architectures Shared Memory Single Address Space Uniform Memory Access (UMA) Non-Uniform Memory Access (NUMA) The Art of Parallel Processing - Siavashi 30

31 AMD Orchi Die Floorplan Based on AMD s Bulldozer Microarchitecture The Art of Parallel Processing - Siavashi 31

32 OpenMP Open Multi-Processing Application Program Interface (API) used to Explicitly direct multi-threaded, shared memory parallelism. The API is specified for C/C++ and Fortran. Most major platforms Unix/Linux platforms Windows The Art of Parallel Processing - Siavashi 32

33 OpenMP (Cont d) Fork Join Model The Art of Parallel Processing - Siavashi 33

34 OpenMP (Cont d) Example. #pragma omp parallel for num_threads(4) for (int i = 0; i < 40; i++) A[i] = i; The Art of Parallel Processing - Siavashi 34

35 Parallel Computer Memory Architectures (Cont d) Distributed Memory No Global Address Space The Art of Parallel Processing - Siavashi 35

36 Computer Cluster The Art of Parallel Processing - Siavashi 36

37 MPI Message Passing Interface Addresses the message-passing parallel programming model data is moved from the address space of one process to that of another process Originally designed for distributed memory architectures The Art of Parallel Processing - Siavashi 37

38 MPI (Cont d) Today, MPI runs on virtually any hardware platform Distributed Memory Shared Memory Hybrid All parallelism is explicit The programmer is responsible for correctly identifying parallelism The Art of Parallel Processing - Siavashi 38

39 MPI (Cont d) Communication Model The Art of Parallel Processing - Siavashi 39

40 MPI (Cont d) Structure The Art of Parallel Processing - Siavashi 40

41 SIMD Single Instruction, Multiple Data A type of parallel computer All processing units execute the same instruction at any given clock cycle Each processing unit can operate on a different data element The Art of Parallel Processing - Siavashi 41

42 GPU Stands for Graphics Processing Unit Integration Scheme: A card on the motherboard NVIDIA GeForce GTX 1080 The Art of Parallel Processing - Siavashi 42

43 NVIDIA CUDA The Art of Parallel Processing - Siavashi 43

44 NVIDIA Fermi The Art of Parallel Processing - Siavashi 44

45 NVIDIA Pascal The Art of Parallel Processing - Siavashi 45

46 How Does It Work? CPU 2. Call Computation 3. Result GPU PC Memory 1. Copy Input Data 4. Copy Result GPU Memory The Art of Parallel Processing - Siavashi 46

47 OpenCL NVIDIA AMD Intel Altera Etc. The Art of Parallel Processing - Siavashi 47

48 The Art of Parallel Processing - Siavashi 48

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