MIPS I/O and Interrupt

Transcription

1 MIPS I/O nd Interrupt

2 Review Floting point instructions re crried out on seprte chip clled coprocessor 1 You hve to move dt to/from coprocessor 1 to do most common opertions such s printing, clling functions, converting number, etc There re 32 floting point registers, $f0 - $f31 You cn ccess ll 32 with single precision instructions You cn only ccess even numbered registers with double precision instructions

3 Review Floting point instructions use the following bbrevitions: s single precision d double precision w integer (word) c1 coprocessor 1 mt/mf move to / move from cvt convert bc1t / bc1f brnch if true/flse c compre

4 Review Questions tht were sked lst clss: Wht delimiter is used to construct n rry of double precision numbers?.double Also,.byte nd.hlf construct rrys of 8bit nd 16bit vlues respectively Cn you move double precision number to word in the min processor? Yes. There is psudo instruction tht moves the vlues from two floting point registers ( double) to two min registers. The first prmeter is min register nd the floting point number is stored here nd in the min register immeditely following it. E.g if you specify $t0, it will store into $t0 nd $t1 mfc1.d $v0, $f0 Other choices vilble: Convert to single precision then move cvt.s.d $f9, $f0 mtc1 $v0, $f9 Sme s the psudo instruction, but cn pick the registers you wnt mtc1 $s0, $f0 mtc1 $t0, $f1 Are there other flgs you cn use in coprocessor 1? Yes, there re 8 flgs you cn use from 0 to 7 Ex. c.le.s 4 $f0, $f1

5 SPIM I/O nd MIPS Interrupts The mterils of this lecture cn be found in A7-A8 (3 rd Edition) nd B7-B8 (4 th Edition). The mteril covered here will only mke brief ppernce on the midterm nd won t be on the finl nor ny exercises / homeworks It is minly used to give you bckground for future clsses such s Computer Orgniztion II nd Operting Systems

6 The MIPS memory Actully, everything bove 0x7fffffff is used by the system.

7 Wht is in there? Specil operting system functions I/O registers mpped to memory ddresses Kernel dt

8 SPIM Input SPIM llows you to red from the keybord (which is similr to reding something from the true I/O register)

9 min: witloop: done:.text.globl min li $s0, 'q' lui $t0, 0xFFFF lw $t1, 0($t0) ndi $t1, $t1, 0x0001 beq $t1, $zero, witloop lw $0, 4($t0) beq $0, $s0, done li $v0,1 syscll li $v0,4 l $0, new_line syscll j witloop li $v0, 10 syscll # q key # $t0 = 0xFFFF0000 # lod control byte # check to see if new dt is there # loop if not # lod dt byte # exit if 'q' is typed # print integer # print string # exit Remember to select ``mpped I/O in PCSpim settings. To set it, select ``Simultor then ``Settings.dt new_line:.sciiz "\n"

10 SPIM output Similr to the input, SPIM hs two memory loctions for output 0xffff0008: Trnsmitter control. Bit 1: interrupt enble Bit 0: redy 0xffff000c: Trnsmitter dt. Bit 0-7: dt byte

11 SPIM output If you need to show something on the console, do the following: 1. Check if redy bit is 1. If yes, proceed. Otherwise, wit. 2. Write to the dt. The redy bit will be reset to 0, nd will be set to 1 fter the byte is trnsmitted.

12 question Is this the most efficient wy to do it? Remember tht the processor usully hs lot of things to do simultneously

13 Interrupt The key problem is tht the time when the input occurs cnnot be predicted by your progrm Wouldn t it be nice if you could focus on wht you re doing while be interrupted if some inputs come?

14 MIPS interrupt With externl interrupt, if n event hppens tht must be processed, the following things will hppen: The ddress of the instruction tht is bout to be executed is sved into specil register clled EPC PC is set to be 0x , the strting ddress of the interrupt hndler which tkes the processor to the interrupt hndler The lst instruction of the interrupt should be eret which sets the vlue of the PC to the vlue stored in EPC 0x : EPC=0x something 0x : dd $t0, $t1, $t0 sub $t2, $t1, $t0 sub $t0 $s0, $0 sll $t0, $t0, 2 dd $k0, $k1, $k0 sub $k1, $k0, $k1 eret...

15 MIPS Interrupt Is it oky to use $t0 in the interrupt? Note the difference between n interrupt nd function cll. For function cll, the cller is wre of the function cll, so, it is not expecting the vlue of $t0 to be the sme fter the cll. For n interrupt, the user progrm is running nd gets interrupted. The user progrm does not know bout the interruption t ll. So, if you chnged $t0 inside n interrupt, fter the interrupt returns, the user progrm will not even be wre of the fct tht it hs been interrupted, nd will use the wrong vlue of $t0. 0x : EPC=0x something 0x : dd $t0, $t1, $t0 sub $t2, $t1, $t0 sub $t0 $s0, $0 sll $t0, $t0, 2 dd $k0, $k1, $k0 sub $t0, $k0, $k1 eret... t0= 10 something 3000

16 MIPS Interrupt $k0 nd $k1 re both used s temporry vribles in interrupt servicing routines.

17 Interrupt Interrupt hndlers should be short. Usully should just use the interrupt to set some flgs, nd let the min progrm to check the flgs Flgs cn be registers nd cn be checked much fster thn reding the vlue of n externl pin or reding dt from other chips

18 .kdt # kernel dt s1:.word 10 s2:.word 11 new_line:.sciiz "\n".text.globl min min: mfc0 $0, $12 ori $0, 0xff11 mtc0 $0, $12 # red from the sttus register # enble ll interrupts # write bck to the sttus register mfc0 $k0, $13 srl $0, $k0, 2 ndi $0, $0, 0x1f bne $0, $zero, kdone lui $v0, 0xFFFF lw $0, 4($v0) li $v0,1 syscll # Cuse register # Extrct ExcCode Field # Get the exception code # Exception Code 0 is I/O. Only processing I/O here # $t0 = 0xFFFF0000 # get the input key # print it here. # Note: interrupt routine should return very fst, so # doing something like print is NOT good prctice! lui $t0, 0xFFFF # $t0 = 0xFFFF0000 li $v0,4 # print the new line ori $0, $0, 2 sw $0, 0($t0) # enble keybord interrupt # write bck to 0xFFFF0000; l $0, new_line syscll here: j here li $v0, 10 syscll.ktext 0x sw $v0, s1 sw $0, s2 # sty here forever # exit,if it ever comes here # kernel code strts here # We need to use these registers # not using the stck becuse the interrupt # might be triggered by memory reference # using bd vlue of the stck pointer kdone: lw $v0, s1 lw $0, s2 mtc0 $0, $13 mfc0 $k0, $12 ndi $k0, 0xfffd ori $k0, 0x11 mtc0 $k0, $12 eret # Restore other registers # Cler Cuse register # Set Sttus register # cler EXL bit # Interrupts enbled # write bck to sttus # return to EPC

19 MIPS interrupt Coprocessor 0 is prt of the CPU to hndle interrupts. In SPIM, Coprocessor 0 contins the BdVAddr (8), storing the memory ddress cusing the exception Count (9), increment by 1 every 10ms by defult Compre (11), if equls to Count, trigger n interrupt of level 5 Sttus (12), Bit 8-15: interrupt msk. A bit being ``1 mens tht this interrupt is enbled. Bit 4: user mode. With SPIM, lwys 1. Bit 1: exception level (EXL). Normlly ``0, set to ``1 if n exception occurred. When ``1, no further interrupt is enbled nd EPC is not updted. Bit 0: interrupt enble. Enble (``1 ) or disble (``0 ) ll interrupts. Cuse (13) Bit 8-15: pending interrupts. A bit being ``1 mens tht this interrupt sitution occurred, even if it is not enbled. Bit 2-6: Exception code. ``0 is hrdwre interrupt. EPC (14) Config (16), config the mchine These registers cn be red nd modified using the instructions mfc0 (move from coprocessor 0) nd mtc0 (move to coprocessor 0).