INTERRUPT, TIMER/COUNTER. KONKUK UNIV. VLSI Design Lab. LSI Design Lab

Transcription

1 INTERRUPT, TIMER/COUNTER KONKUK UNIV. V. 1

2 INTERRUPT 의개요 외부의요구에의해서현재실행중인프로그램을일시중지하고보다시급한작업을먼저수행한후다시원래의프로그램으로복귀하는것. EX) 스타를하다가택배가오면스타를일시중지하고택배를받은후다시스타를진행함. Interrupt 방식 : 택배아저씨가초인종을눌러줌. Polling 방식 : 택배아저씨가오는지일정시간간격으로살펴봄. 2

3 INTERRUPT 의개요 An interrupt is an exception, a change of the normal progression, or interruption in the normal flow of program execution. An interrupt is essentially a hardware generated function call. Interrupts are caused by both internal and external sources. An interrupt causes the normal program execution to halt and for the interrupt service routine (ISR) to be executed. At the conclusion of the ISR, normal program execution is resumed at the point where it was last. Interrupts should be used for infrequent events (1000's of clock cycles) keyboard strokes ms clock ticks serial data (USART, SPI, TWI) Analog to digital conversion uc response time to interrupts is very fast AVR: 4 cycles max 80386: 59 cycles min, 104 cycles max; (0-wait state memory; If response time is really critical, a tight polling loop is used. polling can be faster than interrupts..., but further processing is on hold! 3

4 AVR interrupt servicing 1. In response to the interrupt, the CPU finishes any pending instructions and then ceases fetching further instructions. Global Interrupt Enable (GIE) bit is cleared. 2. Hardware pushes the program counter on the stack. 3. The CPU fetches the instruction from the interrupt vector table that corresponds to the interrupt. This instruction is usually jmp, address. The address is the address of the ISR. 4. The CPU then begins to execute the ISR code. The first part of the ISR is compiler generated code that pushes the status register on the stack as well as any registers that will be used in the ISR. 5. Just before the ISR is done, compiler generated code pops the saved registers as well as the status register. Then the RETI instruction is executed. This restores the program counter from the stack. Global Interrupt Enable bit gets set again. 6. The CPU resumes executing the original instruction stream. 4

5 INTERRUPT 의종류 Reset and Interrupt Vectors Vector NO. Program Address 5 Source 1 $0000(1) RESET Interrupt Definition External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset, and JTAG AVR Reset 2 $0002 INT0 External Interrupt Request 0 3 $0004 INT1 External Interrupt Request 1 4 $0006 INT2 External Interrupt Request 2 5 $0008 INT3 External Interrupt Request 3 6 $000A INT4 External Interrupt Request 4 7 $000C INT5 External Interrupt Request 5 8 $000E INT6 External Interrupt Request 6 9 $0010 INT7 External Interrupt Request 7 10 $0012 TIMER2 COMP Timer/Counter2 Compare Match 11 $0014 TIMER2 OVF Timer/Counter2 Overflow 12 $0016 TIMER1 CAPT Timer/Counter1 Capture Event 13 $0018 TIMER1 COMPA Timer/Counter1 Compare Match A 14 $001A 15 $001C 16 $001E TIMER1 COMPB TIMER1 OVF TIMER0 COMP Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match Vector Program NO. Address Source Interrupt Definition 17 $0020 TIMER0 OVF Timer/Counter0 Overflow 18 $0022 SPI, STC SPI Serial Transfer Complete 19 $0024 USART0, RX USART0, Rx Complete 20 $0026 USART0, UDRE USART0 Data Register Empty 21 $0028 USART0, TX USART0, Tx Complete 22 $002A ADC ADC Conversion Complete 23 $002C EE READY EEPROM Ready 24 $002E ANALOG COMP Analog Comparator 25 $0030 TIMER1 COMPC Timer/Countre1 Compare Match C 26 $0032 TIMER3 CAPT Timer/Counter3 Capture Event 27 $0034 TIMER3 COMPA Timer/Counter3 Compare Match A 28 $0036 TIMER3 COMPB Timer/Counter3 Compare Match B 29 $0038 TIMER3 COMPC Timer/Counter3 Compare Match C 30 $003A TIMER3 OVF Timer/Counter3 Overflow 31 $003C USART1, RX USART1, Rx Complete 32 $003E USART1, UDRE USART1 Data Register Empty 33 $0040 USART1, TX USART1, Tx Complete 34 $0042 TWI Two-wire Serial Interface 35 $0044 SPM READY Store Program Memory Ready

6 INTERRUPT 의종류 Reset and Interrupt Vectors Placement BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 $0000 $ $0000 Boot Reset Address + $ Boot Reset Address $ Boot Reset Address Boot Reset Address + $0002 AVR interrupt vector table All interrupts have separate interrupt vectors in the interrupt vector table Interrupts have priority in accordance with their position in the table. Lower interrupt vector address have higher priority. Reset has top priority. 6

7 INTERRUPT PORT 의연결 INT0~INT7 7

8 Interrupt Vector Select: MCU Control Register MCUCR Bit 1 IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ fuses. Refer to the section Boot Loader Support Read-While-Write Self-Programming on page 276 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Boot Loader Support Read-While-Write Self-Programming on page 276 for details on Boot Lock bits. Bit 0 IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL. 8

9 External Interrupts The External Interrupts are triggered by the INT7:0 pins. If enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in Clock Systems and their Distribution on page 36. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. 9

10 External Interrupts Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25 C. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics on page 322. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in Clock Systems and their Distribution on page 36. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. 10

11 Interrupts registers External Interrupt Control Register A EICRA External Interrupt Control Register B EICRB External Interrupt Mask Register EIMSK External Interrupt Flag Register EIFR 11

12 INTERRUPT REGISTER - EICRA External Interrupt Control Register A EICRA 모든인터럽트는 GLOBAL INTERRUPT가 ENABLE 되어야작동함. 외부인터럽트제어레지스터 A : EICRA (INT0~INT3) This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level interrupts, as in ATmega103. Bits 7..0 ISC31, ISC30 ISC00, ISC00: External Interrupt 3-0 Sense Control Bits The External Interrupts 3-0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is reenabled. 12

13 INTERRUPT REGISTER - EICRA Interrupt Sense Control (1) ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request. 0 1 Reserved 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: 1. n = 3, 2, 1or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. Asynchronous External Interrupt Characteristics 13

14 INTERRUPT REGISTER - EICRB 외부인터럽트제어레지스터 B : EICRB (INT4~INT7) Bits 7..0 ISC71, ISC70 - ISC41, ISC40: External Interrupt 7-4 Sense Control Bits The External Interrupts 7-4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 50. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. 14

15 INTERRUPT REGISTER - EICRB Interrupt Sense Control (1) ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge between two samples of INTn generates an interrupt request. 1 1 The rising edge between two samples of INTn generates an interrupt request. n = 7, 6, 5 or 4. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. 15

16 INTERRUPT REGISTER - EIMSK External Interrupt Mask Register EIMSK 외부인터럽트마스크레지스터 : EIMSK 어떤입력을인터럽트로사용할지를설정. Bits 7..0 INT7 INT0: External Interrupt Request 7-0 Enable When an INT7 INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 16

17 INTERRUPT REGISTER - EIFR External Interrupt Flag Register EIFR 외부인터럽트플래그레지스터 : EIFR INT0~INT7 중에해당인터럽트가트리거되었음을표시하는데사용. 해당인터럽트서비스루틴으로점프하게되면 0 으로설정됨. Bits 7..0 INTF7 - INTF0: External Interrupt Flags 7 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. 17

18 INTERRUPT EXAMPLE INT4 버튼이눌러질때마다 LED 가 on, off 를반복하는프로그램. Interrupt 4 LED1 LED2 LED3 LED4 18 LED1 LED2 LED3 LED4

19 2. TIMER/ COUNTER 19

20 TIMER/COUNTER 의개요 입력으로들어오는신호 ( 펄스 ) 를세는장치이며입력신호의소스가내부클럭에의존하면타이머이고, 외부핀으로들어오는신호에의존하면카운터가된다. ATmega128 은 4 개의 TIMER/COUNTER 로구성된다. Timer/Counter0(8 비트 ), Timer/Counter1(16 비트 ), Timer/Counter2(8 비트 ), Timer/Counter3(16 비트 ) OVERFLOW INTERRUPT 카운터값이오버플로우된경우발생. 20

21 TIMER/COUNTER 의개요 Timer/Counter0 내부클럭혹은외부클럭을모두사용가능. 외부클럭을사용할경우비동기모드로동작가능. 프리스케일러적용가능. ** 프리스케일러 : 타이머에입력되는클럭의속도를조절할수있는분주기. Timer/Counter1~3 내부클럭사용. 프리스케일러적용가능. 21

22 Block Diagram of 8bit TIMER/COUNTER 22

23 Block Diagram of Output Compare Unit/OCxy Pins 23

24 TIMER/COUNTER REGISTER Timer/Counter Control Register TCCR0 Timer/Counter Register TCNT0 Output Compare Register OCR0 Asynchronous Status Register ASSR Timer/Counter Interrupt Mask Register TIMSK Timer/Counter Interrupt Flag Register TIFR 24

25 TIMER/COUNTER REGISTER TCCR0 TIMER/COUNTER 제어레지스터 : TCCR0 Bit 7 FOC0: Force Output Compare FOC0 : 1 로설정할경우즉시강제로 OC0 단자에비교매치 (compare match) 신호를출력. OSR0 에어떤값을써준후 Timer/Counter0 가 OSR0 의값과같아질때 OC0 단자 (PB4) 를 toggle, set, clear 시킬수있다. The FOC0 bit is only active when the WGM bits specify a non-pwm mode. For ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. 25

26 TIMER/COUNTER REGISTER TCCR0 TIMER/COUNTER 제어레지스터 : TCCR0 Bit 6, 3 WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. 26

27 TIMER/COUNTER REGISTER TCCR0 cont. WGM00~01 Waveform Generation Mode 어떤파형을발생시킬지를결정 Normal Mode : 255 까지카운터한뒤인터럽트발생. CTC (Clear Timer on Compare match) : 인터럽트를발생시키는최대카운터수를설정. Fast PWM Mode : 최대카운터수이전에인터럽트발생설정. PCPWM (Phase Correct Pulse Width Modulation) : 최대카운터수로부터 0 까지역순으로카운트. 27

28 TIMER/COUNTER REGISTER TCCR0 cont. Bit 5:4 COM01:0: Compare Match Output Mode: COM00~01 Compare Match Output Mode OC0 단자에비교매치를출력. These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non- PWM). Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. 28

29 TIMER/COUNTER REGISTER TCCR0 cont. Bit 2:0 CS02:0: Clock Select: CS02~CS00 : PRESCALER의설정 The three clock select bits select the clock source to be used by the Timer/Counter. Clock Select Bit Description 29

30 TIMER/COUNTER REGISTER TCNT0 TIMER/COUNTER 제어레지스터 : TCNT0 8bit 카운터값을저장. The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0 Register. TIMER/COUNTER 제어레지스터 : OCR0 TCNT0 값과비교하여 OC0 단자에출력신호를발생하기위한 8bit 값을저장. 30

31 TIMER/COUNTER REGISTER OCR0 TIMER/COUNTER 제어레지스터 : OCR0 TCNT0 값과비교하여 OC0 단자에출력신호를발생하기위한 8bit 값을저장. The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. 31

32 TIMER/COUNTER REGISTER - ASSR TIMER/COUNTER 제어레지스터 : ASSR 외부클럭에의하여비동기모드로동작하는경우관련기능을수행. Bit 3 AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clki/o. When AS0 is written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted. Bit 2 TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value. 32

33 TIMER/COUNTER REGISTER - ASSR TIMER/COUNTER 제어레지스터 : ASSR Bit 1 OCR0UB: Output Compare Register0 Update Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value. Bit 0 TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read. 33

34 TIMER/COUNTER REGISTER - TIMSK TIMER/COUNTER 제어레지스터 : TIMSK Bit 1 OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable 1 로설정되고, 상태레지스터 (SREG) 의 I-bit 이 1 로설정될경우작동. 이렇게설정된상태에서 TIFR 의 OCF0 가 1 이되면이인터럽트가처리됨. Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable TOIE0 : 1 로설정되고, SREG 의 I-bit 이 1 이로설정되면 Overflow interrupt 가 enable 됨. 34

35 TIMER/COUNTER REGISTER - TIFR TIMER/COUNTER 인터럽트플래그레지스터 : TIFR Bit 1 OCF0: Output Compare Flag 0 OCF0 : Timer/Counter0 와 OCR0 의데이터사이에비교매치가발생한경우 1 로설정된다. 인터럽트가처리된후 clear 된다. Bit 0 TOV0: Timer/Counter0 Overflow Flag TOV0 : Overflow 가발생한경우 1 로설정된다. 인터럽트가처리된후 clear 된다. 35

36 Prescaler of Timer/Counter0 The clock source for Timer/Counter0 is named clkt0. clkt0 is by default connected to the main system clock clki/o. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter0. The Oscillator is optimized for use with a khz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter0, the possible prescaled selections are: clkt0s/8, clkt0s/32, clkt0s/64, clkt0s/128, clkt0s/256, and clkt0s/1024. Additionally, clkt0s as well as 0 (stop) may be selected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler

37 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: True 16-bit Design (i.e.,allows 16-bit PWM) Three Independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B, OCF3C, and ICF3) 37

38 Training board - External Interrupt Switches Hardware Interrupt using External Switches. In the training board, there are 2 switches which are connected to INT4 and INT5 of AVR

39 TIMER EXAMPLE 39

40 HW#1 INTERRUPT (UP AND DOWN) INT4 SW 를누르면 up 카운트가되고 INT5 SW 를누르면 down 카운트가되게만든다. 40

41 HW#2 INTERRUPT (start&stop, up&down) INT4 스위치를누르면 0000 셋팅에서일자리부터증가 START(1->2->3->4 ), 다시누르면증가 STOP. INT5 스위치를누르면 UP 카운팅, 다시누르면 DOWN 카운팅되도록한다. 41

42 HW#3 INTERRUPT (Stop Watch) 7-Segment 와 Timer Interrupt 를사용하여정확한 Stop Watch 를구현할것. INT4를누를경우 START 동작중에 INT4를누를경우 STOP 동작중에 INT5를누를경우 RESET( 계속동작 ) 정지상태에서 INT4를누를경우 START 정지상태에서 INT5를누를경우 RESET 42