CMSC Computer Architecture Lecture 18: Exam 2 Review Session. Prof. Yanjing Li University of Chicago

Transcription

1 CMSC Computer Architecture Lecture 18: Exam 2 Review Session Prof. Yanjing Li University of Chicago

2 Administrative Stuff! Lab 5 (multi-core) " Due: 11:59pm, Dec. 1 st, Thursday " Two late days with penalty " TAs are holding Labs tomorrow! Exam 2, Wednesday, 11/30, 7-9pm, Kent 107 " Open book, open notes, close electronic device " A calculator can be handy 2

3 Administrative Stuff! My office hours this week " Additional office hours! Tuesday(11/29): 1-3pm! Wednesday(11/30): 10:30-11:30am, 1-3pm " Office hours on Thursday moved to 9:30am-10:30am! All TAs are holding their normal office hours 3

4 Where Are We in the Lecture Schedule?! ISA! Uarch " Datapath, control " Single cycle, multi cycle! Pipelining: basic, dependency handling, branch prediction! Advanced uarch: OOO, SIMD, VLIW, superscalar! Caches and advanced caches! Multi-core! Virtual memory, main memory (DRAM)! Last lecture " Exceptions/interrupts, I/O, wrap-up 4

5 Exam 2 Topics! Microarcthiecture techniques to improve ILP " OOO: Tomasulo s algorithm, register renaming, reservation stations, memory disambiguation " SIMD and VLIW! Caches " Basics, design considerations and tradeoffs, advanced techniques! Multi-core " Benefits, parallel programs, Amdahl s law (speedup), cache coherence, memory consistency, synchronization! Virtual memory " How it works, page tables, page fault, TLB, interaction with L1 caches! Main memory (DRAM)! Everything covered in Exam 1 5

6 We did not cover the following topics. The slides are posted for your benefit.

7 Lecture Outline! Exceptions and interrupts! I/O 7

8 Exceptions and Interrupts! Unscheduled change of the normal instruction flow! Exceptions " Internal to the running thread " Associated with a particular instruction " Examples: divide-by-0, undefined machine code, page fault! Interrupts " External to the running thread " Not associated with any instruction " Examples: I/O device request, system reset 8

9 When to Handle?! Exceptions " When detected (and known to be non-speculative) " In the 5-stage ARMv8 pipeline processor, in which stage can we detect the following exceptions?! Divide-by-0, undefined machine code, page fault! Interrupts " When convenient " Except for very high priority ones! Power failure! Machine check (error)! Priorities and timing behavior defined in ISA 9

10 Precise Exceptions! The architectural state should be consistent when the exception/interrupt is ready to be handled 1. All previous instructions should be completely retired. 2. No later instruction should be retired. Retire = commit = finish execution and update arch. state 10

11 Why Do We Want Precise Exceptions?! Semantics of the von Neumann model ISA specifies it! Aids software debugging " Think about breakpoints; how useful are they if we don t have precise exceptions?! Enables (easy) recovery from exceptions " e.g. page faults; restart from the faulting instruction after it s handled 11

12 Providing Precise Exceptions! In-order 5-stage pipeline t 0 t 1 t 2 t 3 t 4 t 5 Inst h IF PC ID EX killed Inst i Inst j IF PC+4 ID IF PC+8 killed killed Inst k Inst l IF ID IF EX ID IF WB EX ID IF Inst k is the first instrucaon of the excepaon handling rouane 12

13 Providing Precise Exceptions! How about out-of-order execution?! Or, in-order dispatch/execution, out-of-order completion? FMUL R4 # R1, R2 ADD R3 # R1, R2 FMUL R2 # R5, R6 ADD R7 # R5, R6 F D E E E E E E E E W F D E W F D E W F D E W F D E E E E E E E E W F D E W F D E W! Use a reorder buffer! 13

14 Reorder Buffer (ROB)! Idea: Complete instructions out-of-order, but reorder them before making results visible to architectural state! When instruction is decoded it reserves an entry in the ROB! When instruction completes, it writes result into ROB entry! When instruction oldest in ROB and it has completed without exceptions, its result moved to reg. file or memory Func Unit Instruction Cache Register File Func Unit Reorder Buffer Func Unit 14

15 What s in a ROB Entry? V DestRegID DestRegVal StoreAddr StoreData PC Valid bits for reg/data + control bits Exc? 15

16 Exception/Interrupt Handling Mechanism! Hardware and software work together! Hardware " Provide precise exception semantics " Record relevant information (e.g., PC of the faulting instruction, cause of the exception/interrupt, etc.) " Jump to exception/interrupt handling routine! Software (OS) " Implement & install exception/interrupt handling routine " i.e., OS determines how to handle exceptions/interrupts 16

17 Example: ARMv8! Address of the unlucky instruction saved in a register " ELR, exception link register! Reason of exception/interrupt saved in a register " ESR, exception syndrome register! Processor jumps to a predefined address " Single entry point for all exceptions/interrupts! OS takes appropriate actions based on ESR, and restarts execution by jumping back to ELR if needed 17

18 Example: x86! Vectored interrupt! Key data structure: interrupt descriptor table (IDT) " Each IDT entry: entry point of an exception/interrupt routine " The type of the exception determines the index to the table " OS fills the IDT entries 18

19 I/O Many I/O controllers (highlighted) 19

20 What Instructions to Use for I/O operations?! Special I/O instructions " E.g., in and out in x86! Regular load/store instructions " Memory-mapped I/O 20

21 Two I/O Mechanisms! Programmed I/O (PIO) " CPU issues instruction to perform I/O operations! Direct Memory Access (DMA) " CPU specifies what I/O operations need to be performed, an a dedicated hardware controller (the DMA controller) performs the operation to free up the CPU so that it can perform other tasks 21