Interrupts Peter Rounce
|
|
- Marian Hampton
- 6 years ago
- Views:
Transcription
1 Interrupts Peter Rounce 22/11/ GC03 Interrupts 1
2 INTERRUPTS An interrupt is a signal to the CPU from hardware external to the CPU that indicates than some event has occured, e.g. data has arrived at an input interface. CPUs respond to an interrupt by switching from executing the instructions of the current program to executing instructions to handle the event that caused the interrupt. The interrupt mechanism provides an efficient way to detect the occurrence of an event. It is important to understand the implementation of interrupts and when they should or should not be used. Interrupts are a key element in the operation of most computer systems. 22/11/ GC03 Interrupts 2
3 Why interrupts? Polling is inefficient when data rates are low: - too many CPU cycles wasted executing instructions of polling loop. Polling is the wrong approach to handling events where the time of the occurrence of an event is uncertain or distant, i.e. 100s of clock cycles away. Start Read Status Register Start Read Status Register The occurrence of the event should be the trigger for CPU action, the CPU should not be checking for the event. Examples of similar systems: a knock on the door, the ringing of the telephone Buffer Full? Y Read Data from Data Port Buffer Empty? Y Write Data intodata Port 22/11/ GC03 Interrupts 3 End N End Example polling software on input and output interfaces N
4 Points to cover:- how is interrupt signal generated how are interrupts prioritised, if there are several at same time how does CPU identify event that generated interrupt how does CPU switch from to running software to deal with event how is it that program running at time of interrupt is not affected how does interrupt software exchange data with rest of system 22/11/ GC03 Interrupts 4
5 8-Bit Parallel Output Interface READ 8-Bit Parallel Input Interface READ Data Bus WRITE interrupt Data Reg Status Reg Output Data Input Data Flow Control Signals Data Reg Status Reg Data Bus interrupt Address Bus Select Signals Select Signals Address Bus When Rx acknowledges receipt of data the TX interrupt request is activated Writing new data into the Data Register or reading Status Register deactivates TX interrupt request Arrival of new data triggers activation of interrupt request Reading data from Data Register deactivates interrupt request 22/11/ GC03 Interrupts 5
6 I/O INT Interface INTERRUPT HARDWARE To I/O devices I/O INT Interface I/O INT Interface I 1 I 2 I 3 I n Interrupt Controller Interrupt Request Interrupt CPU I/O INT Interface Data Bus Decoder Address Bus Data Bus 1) I/O interface generates an interrupt request signal on some Tx or Rx event. 2) Interrupt Controller generates an interrupt request to CPU, when one or more inputs is active. 3) CPU reads Interrupt Controller to get number (vector) identifying the highest priority active interrupt request (priority in by input number, or rotating priority allocation: the vector identifies the highest priority interrupt device requiring service. [This is why the controller is shown with connections to the system busses:to read vector] 22/11/ GC03 Interrupts 6
7 CPU Activity in servicing an Interrupt Request When Interrupt Request becomes active, CPU completes current instruction, and then executes the following operations automatically:- CPU saves PC register & turns off interrupts CPU loads PC with new value CPU resumes instruction processing CPU switches to execute software in response to the interrupt. Software handles event that occurred, e.g. data received. This software is called the Interrupt Service Routine (ISR). At end of ISR, CPU continues the interrupted program. Alternatives: Once in the ISR, software can determine whether to return to the interrupted program, to suspend it or to close it down. ISR now executes to deal with event generating interrupt until... CPU resumes instruction processing of interrupted program at end of ISR CPU loads registers and PC with values saved at start of interrupt service, a special return-frominterrupt instruction is executed to re-enable interrupts 22/11/ GC03 Interrupts 7
8 Another way of viewing of Interrupt Servicing Instructions of program being executed by CPU Interrupt Service Routine (ISR) general structure Interrupt Request PC saved, PC loaded with new value further interrupts disabled PC reloaded Interrupts re-enabled Save CPU registers changed in ISR Handle event that caused interrupt, e.g. input data, output data acknowledged. Restore CPU registers saved at start of ISR Return-from-interrupt Instruction executed Interrupt is very like a hardware generated function call! Saving/restoring registers ensures state of interrupted program is not changed by interrupt servicing. stack is used to save state 22/11/ GC03 Interrupts 8
9 Where does new PC address come from? Non-vectored interrupts: new PC address is defined in CPU hardware, always go to same address: find source of event by polling IO interfaces slow! Vectored Interrupts: Vector read from controller is used to look up the address of software to handle interrupt, and placed in PC. This activity is done by the hardware. This allows CPU to get quickly to the software to handle the event. The interrupt table has to be set up by software. vector PC Interrupt table in memory MIPS uses Non-vectored interrupt, so ISR is found by software. 22/11/ GC03 Interrupts 9
10 Interrupt are very good for low frequency data. There is a large overhead in saving and restoring program state (registers & PC), which limits the maximum frequency of data that can be handled. 22/11/ GC03 Interrupts 10
11 How does ISR handle interrupt event? One way is to use circular buffers to queue data Input Device: Output Device: ISR puts input data on to tail of queue in circular buffer. Data producer program puts output data into tail of queue. data removed by consumer program from head of queue at convenient time data removed from head of queue by ISR and output 22/11/ GC03 Interrupts 11
12 Timer Device CPU writes count into count-down register and starts counting by writing into a control register in the timer. Register counted down by one on each clock rising edge. When count register reaches zero, interrupt generated and register reloaded. Clock Count-down register written over data bus by software: once written, the count will be restored once zero is reached. Timer looks like I/O device to CPU. Timer Device Control Register Count-down Register Decoder Address Bus Data Bus Interrupt Request Timer generates interrupts at regular time intervals. Instead of re-starting interrupted program after timer interrupt, operating system may suspend this program and switch to run another program. Thus, each program is executed for a time slice at regular intervals: this is how an operating system runs several programs at once. 22/11/ GC03 Interrupts 12
13 Switching processes on interrupt in an operating system environment, e.g. linux. Instructions of program X being executed by CPU Timer Interrupt Request Switch to running ISR Load program B state from program B stack ISR Instructions of program Y in memory as well. Save all program A state on its stack Switch to run program at end of ISR On any interrupt, but particularly on a timer interrupt, the operating can store the state of the interrupted program, i.e. the register contents, on the program stack. It can then resume the execution of a previously suspended program or even start the execution of a new program (usually called a process). In this way, the operating system can seem to be executing several processes at a time by running allowing one process to execute on the CPU for short period (a time slice ) before suspending the process and allowing another process to run. The ISRs are considered part of the operating system. A process can be suspended for a long while while awaiting some I/O activity to complete. 22/11/ GC03 Interrupts 13
14 Exceptions These are very similar to interrupts in many ways. Exceptions are caused by the current instruction being executed. Interrupts are always triggered outside the CPU and are caused by events that are being awaited e.g. an I/O transfer completing, a timer count elapsing. Exceptions are either triggered inside the CPU or is caused by an error condition on a transfer to memory or I/O interface. The last is signalled via BUS ERROR input to the CPU. Internal CPU exceptions are often error conditions, e.g. divide-by-zero exception, an address error (perhaps an odd address where an even one is expected) An exception is processed in an exactly similar way to an Interrupt except that the vector used to look up the vector table is generated by the CPU. Exceptions are generally triggered by software actions rather than hardware events. 22/11/ GC03 Interrupts 14
15 System Call Exception the exception that is an NOT an error Used in a computer with a protection system to allow a user program to call a particular service in the operating system to perform a privileged operation. Example services: open a file for reading or writing reading or writing data to an open file write data to the screen allocate some space on the heap. All these are activities for which could corrupt the system, breach security User Code:- Set up data on stack for service required Set identifier for service Execute system call instruction sc, trap system call exception generated; exception service routine for a system call executed When service completes the user program will continue as if a method/function/subroutine call had been made 22/11/ GC03 Interrupts 15
16 MIPS Operation On interrupt/exception: Hardware operations wait for completion of current instruction save pc to epc register (exception program counter register) set type of event in cause register load pc with address restart execution MIPS Exceptions address error exception on load address error exception on load bus error on instruction fetch bus error on data load or store system call exception breakpoint exception reserved instruction exception arithmetic overflow exception Interrupt/Exception Service Routine resides at address 0x The ISR must discover the cause of the event and then execute software to deal with the event. It is the ISR responsibility to save the state (register values) of the interrupted program if this program is to be continued later. If interrupt occurred, then must discover what device generated it. 22/11/ GC03 Interrupts 16
Interrupts Peter Rounce - room 6.18
Interrupts Peter Rounce - room 6.18 P.Rounce@cs.ucl.ac.uk 20/11/2006 1001 Interrupts 1 INTERRUPTS An interrupt is a signal to the CPU from hardware external to the CPU that indicates than some event has
More informationOperating System Control Structures
Operating System Control Structures Information about the current status of each process and resource Tables are constructed for each entity the operating system manages 26 Memory Tables Allocation of
More informationInput / Output. School of Computer Science G51CSA
Input / Output 1 Overview J I/O module is the third key element of a computer system. (others are CPU and Memory) J All computer systems must have efficient means to receive input and deliver output J
More informationInput Output (IO) Management
Input Output (IO) Management Prof. P.C.P. Bhatt P.C.P Bhatt OS/M5/V1/2004 1 Introduction Humans interact with machines by providing information through IO devices. Manyon-line services are availed through
More informationProcess Description and Control
Process Description and Control 1 summary basic concepts process control block process trace process dispatching process states process description process control 2 Process A program in execution (running)
More informationThe control of I/O devices is a major concern for OS designers
Lecture Overview I/O devices I/O hardware Interrupts Direct memory access Device dimensions Device drivers Kernel I/O subsystem Operating Systems - June 26, 2001 I/O Device Issues The control of I/O devices
More informationProcess Description and Control. Major Requirements of an Operating System
Process Description and Control Chapter 3 1 Major Requirements of an Operating System Interleave the execution of several processes to maximize processor utilization while providing reasonable response
More informationMajor Requirements of an Operating System Process Description and Control
Major Requirements of an Operating System Process Description and Control Chapter 3 Interleave the execution of several processes to maximize processor utilization while providing reasonable response time
More informationCSC227: Operating Systems Fall Chapter 1 INTERRUPTS. Dr. Soha S. Zaghloul
CSC227: Operating Systems Fall 2016 Chapter 1 INTERRUPTS Dr. Soha S. Zaghloul LAYOUT 1.3 Devices Controlling Techniques 1.3.1 Polling 1.3.2 Interrupts H/W Interrupts Interrupt Controller Process State
More informationMajor Requirements of an OS
Process CSCE 351: Operating System Kernels Major Requirements of an OS Interleave the execution of several processes to maximize processor utilization while providing reasonable response time Allocate
More informationProcess Description and Control. Chapter 3
Process Description and Control Chapter 3 Contents Process states Process description Process control Unix process management Process From processor s point of view execute instruction dictated by program
More informationProcess Description and Control
Process Description and Control Chapter 3 Muhammad Adri, MT 1 Major Requirements of an Operating System Interleave the execution of several processes to maximize processor utilization while providing reasonable
More information18-349: Introduction to Embedded Real-Time Systems
18-349: Introduction to Embedded Real-Time Systems Embedded Real-Time Systems Lecture 6: Timers and Interrupts Anthony Rowe Electrical and Computer Engineering Carnegie Mellon University Embedded Real-Time
More informationOperating Systems. Lecture 3- Process Description and Control. Masood Niazi Torshiz
Operating Systems Lecture 3- Process Description and Control Masood Niazi Torshiz www.mniazi.ir 1 Requirements of an Operating System Interleave the execution of multiple processes to maximize processor
More informationThese three counters can be programmed for either binary or BCD count.
S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers.
More informationVirtual Memory Outline
Virtual Memory Outline Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory Other Considerations Operating-System Examples
More informationCS 550 Operating Systems Spring Interrupt
CS 550 Operating Systems Spring 2019 Interrupt 1 Revisit -- Process MAX Stack Function Call Arguments, Return Address, Return Values Kernel data segment Kernel text segment Stack fork() exec() Heap Data
More informationChapter 9: Virtual Memory
Chapter 9: Virtual Memory Silberschatz, Galvin and Gagne 2013 Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating
More informationPC Interrupt Structure and 8259 DMA Controllers
ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 PC Interrupt Structure and 8259 DMA Controllers This lecture covers the use of interrupts and the vectored interrupt
More informationCMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013
CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 09, SPRING 2013 TOPICS TODAY I/O Architectures Interrupts Exceptions FETCH EXECUTE CYCLE 1.7 The von Neumann Model This is a general
More information1. Background. 2. Demand Paging
COSC4740-01 Operating Systems Design, Fall 2001, Byunggu Yu Chapter 10 Virtual Memory 1. Background PROBLEM: The entire process must be loaded into the memory to execute limits the size of a process (it
More informationInf2C - Computer Systems Lecture 16 Exceptions and Processor Management
Inf2C - Computer Systems Lecture 16 Exceptions and Processor Management Boris Grot School of Informatics University of Edinburgh Class party! When: Friday, Dec 1 @ 8pm Where: Bar 50 on Cowgate Inf2C Computer
More informationCPS104 Computer Organization and Programming Lecture 17: Interrupts and Exceptions. Interrupts Exceptions and Traps. Visualizing an Interrupt
CPS104 Computer Organization and Programming Lecture 17: Interrupts and Exceptions Robert Wagner cps 104 Int.1 RW Fall 2000 Interrupts Exceptions and Traps Interrupts, Exceptions and Traps are asynchronous
More informationOperating Systems. Introduction & Overview. Outline for today s lecture. Administrivia. ITS 225: Operating Systems. Lecture 1
ITS 225: Operating Systems Operating Systems Lecture 1 Introduction & Overview Jan 15, 2004 Dr. Matthew Dailey Information Technology Program Sirindhorn International Institute of Technology Thammasat
More informationIT 540 Operating Systems ECE519 Advanced Operating Systems
IT 540 Operating Systems ECE519 Advanced Operating Systems Prof. Dr. Hasan Hüseyin BALIK (3 rd Week) (Advanced) Operating Systems 3. Process Description and Control 3. Outline What Is a Process? Process
More informationChapter 9: Virtual-Memory
Chapter 9: Virtual-Memory Management Chapter 9: Virtual-Memory Management Background Demand Paging Page Replacement Allocation of Frames Thrashing Other Considerations Silberschatz, Galvin and Gagne 2013
More informationUnit 3 and Unit 4: Chapter 4 INPUT/OUTPUT ORGANIZATION
Unit 3 and Unit 4: Chapter 4 INPUT/OUTPUT ORGANIZATION Introduction A general purpose computer should have the ability to exchange information with a wide range of devices in varying environments. Computers
More informationAnne Bracy CS 3410 Computer Science Cornell University
Anne Bracy CS 3410 Computer Science Cornell University The slides were originally created by Deniz ALTINBUKEN. P&H Chapter 4.9, pages 445 452, appendix A.7 Manages all of the software and hardware on the
More informationLecture 3: Concurrency & Tasking
Lecture 3: Concurrency & Tasking 1 Real time systems interact asynchronously with external entities and must cope with multiple threads of control and react to events - the executing programs need to share
More informationAnne Bracy CS 3410 Computer Science Cornell University
Anne Bracy CS 3410 Computer Science Cornell University The slides were originally created by Deniz ALTINBUKEN. P&H Chapter 4.9, pages 445 452, appendix A.7 Manages all of the software and hardware on the
More informationby I.-C. Lin, Dept. CS, NCTU. Textbook: Operating System Concepts 8ed CHAPTER 13: I/O SYSTEMS
by I.-C. Lin, Dept. CS, NCTU. Textbook: Operating System Concepts 8ed CHAPTER 13: I/O SYSTEMS Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests
More information操作系统概念 13. I/O Systems
OPERATING SYSTEM CONCEPTS 操作系统概念 13. I/O Systems 东南大学计算机学院 Baili Zhang/ Southeast 1 Objectives 13. I/O Systems Explore the structure of an operating system s I/O subsystem Discuss the principles of I/O
More informationProcess Scheduling Queues
Process Control Process Scheduling Queues Job queue set of all processes in the system. Ready queue set of all processes residing in main memory, ready and waiting to execute. Device queues set of processes
More informationHardware OS & OS- Application interface
CS 4410 Operating Systems Hardware OS & OS- Application interface Summer 2013 Cornell University 1 Today How my device becomes useful for the user? HW-OS interface Device controller Device driver Interrupts
More informationQ.1 Explain Computer s Basic Elements
Q.1 Explain Computer s Basic Elements Ans. At a top level, a computer consists of processor, memory, and I/O components, with one or more modules of each type. These components are interconnected in some
More informationThere are different characteristics for exceptions. They are as follows:
e-pg PATHSHALA- Computer Science Computer Architecture Module 15 Exception handling and floating point pipelines The objectives of this module are to discuss about exceptions and look at how the MIPS architecture
More informationHakim Weatherspoon CS 3410 Computer Science Cornell University
Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Deniz Altinbuken, Professors Weatherspoon, Bala, Bracy, and Sirer. C practice
More informationToday s class. Finish review of C Process description and control. Informationsteknologi. Tuesday, September 18, 2007
Today s class Finish review of C Process description and control Computer Systems/Operating Systems - Class 6 1 Finish review of C Review in class exercise 3 #1: game cptr is 5004 #2: The value of c is
More informationProcess- Concept &Process Scheduling OPERATING SYSTEMS
OPERATING SYSTEMS Prescribed Text Book Operating System Principles, Seventh Edition By Abraham Silberschatz, Peter Baer Galvin and Greg Gagne PROCESS MANAGEMENT Current day computer systems allow multiple
More informationChapter 8: Virtual Memory. Operating System Concepts Essentials 2 nd Edition
Chapter 8: Virtual Memory Silberschatz, Galvin and Gagne 2013 Chapter 8: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating
More informationEfficiency and memory footprint of Xilkernel for the Microblaze soft processor
Efficiency and memory footprint of Xilkernel for the Microblaze soft processor Dariusz Caban, Institute of Informatics, Gliwice, Poland - June 18, 2014 The use of a real-time multitasking kernel simplifies
More informationComputer Systems II. First Two Major Computer System Evolution Steps
Computer Systems II Introduction to Processes 1 First Two Major Computer System Evolution Steps Led to the idea of multiprogramming (multiple concurrent processes) 2 1 At First (1945 1955) In the beginning,
More informationAnnouncement. Exercise #2 will be out today. Due date is next Monday
Announcement Exercise #2 will be out today Due date is next Monday Major OS Developments 2 Evolution of Operating Systems Generations include: Serial Processing Simple Batch Systems Multiprogrammed Batch
More informationProcesses. Dr. Yingwu Zhu
Processes Dr. Yingwu Zhu Process Growing Memory Stack expands automatically Data area (heap) can grow via a system call that requests more memory - malloc() in c/c++ Entering the kernel (mode) Hardware
More information8086 Interrupts and Interrupt Responses:
UNIT-III PART -A INTERRUPTS AND PROGRAMMABLE INTERRUPT CONTROLLERS Contents at a glance: 8086 Interrupts and Interrupt Responses Introduction to DOS and BIOS interrupts 8259A Priority Interrupt Controller
More information3.1 Introduction. Computers perform operations concurrently
PROCESS CONCEPTS 1 3.1 Introduction Computers perform operations concurrently For example, compiling a program, sending a file to a printer, rendering a Web page, playing music and receiving e-mail Processes
More informationCS370 Operating Systems
CS370 Operating Systems Colorado State University Yashwant K Malaiya Spring 2018 L20 Virtual Memory Slides based on Text by Silberschatz, Galvin, Gagne Various sources 1 1 Questions from last time Page
More informationChe-Wei Chang Department of Computer Science and Information Engineering, Chang Gung University
Che-Wei Chang chewei@mail.cgu.edu.tw Department of Computer Science and Information Engineering, Chang Gung University l Chapter 10: File System l Chapter 11: Implementing File-Systems l Chapter 12: Mass-Storage
More informationOPERATING SYSTEMS. Systems with Multi-programming. CS 3502 Spring Chapter 4
OPERATING SYSTEMS CS 3502 Spring 2018 Systems with Multi-programming Chapter 4 Multiprogramming - Review An operating system can support several processes in memory. While one process receives service
More informationProgramming Embedded Systems
Programming Embedded Systems Lecture 5 Interrupts, modes of multi-tasking Wednesday Feb 1, 2012 Philipp Rümmer Uppsala University Philipp.Ruemmer@it.uu.se 1/31 Lecture outline Interrupts Internal, external,
More informationModule 3. Embedded Systems I/O. Version 2 EE IIT, Kharagpur 1
Module 3 Embedded Systems I/O Version 2 EE IIT, Kharagpur 1 Lesson 15 Interrupts Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would learn Interrupts
More informationHANDLING MULTIPLE DEVICES
HANDLING MULTIPLE DEVICES Let us now consider the situation where a number of devices capable of initiating interrupts are connected to the processor. Because these devices are operationally independent,
More informationCS 104 Computer Organization and Design
CS 104 Computer Organization and Design Exceptions and Interrupts CS104: Exceptions and Interrupts 1 Exceptions and Interrupts App App App System software Mem CPU I/O Interrupts: Notification of external
More informationPage Replacement Algorithms
Page Replacement Algorithms MIN, OPT (optimal) RANDOM evict random page FIFO (first-in, first-out) give every page equal residency LRU (least-recently used) MRU (most-recently used) 1 9.1 Silberschatz,
More informationChapter 8: Virtual Memory. Operating System Concepts
Chapter 8: Virtual Memory Silberschatz, Galvin and Gagne 2009 Chapter 8: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems DM510-14 Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations STREAMS Performance 13.2 Objectives
More informationINTERRUPTS in microprocessor systems
INTERRUPTS in microprocessor systems Microcontroller Power Supply clock fx (Central Proccesor Unit) CPU Reset Hardware Interrupts system IRQ Internal address bus Internal data bus Internal control bus
More informationModule 12: I/O Systems
Module 12: I/O Systems I/O hardwared Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Performance 12.1 I/O Hardware Incredible variety of I/O devices Common
More informationEE458 - Embedded Systems Exceptions and Interrupts
EE458 - Embedded Systems Exceptions and Interrupts Outline Exceptions Interrupts References RTC: Chapters 10 CUG: Chapters 8, 21, 23 1 Introduction An exception is any event that disrupts the normal execution
More informationSyscalls, exceptions, and interrupts, oh my!
Syscalls, exceptions, and interrupts, oh my! Hakim Weatherspoon CS 3410 Computer Science Cornell University [Altinbuken, Weatherspoon, Bala, Bracy, McKee, and Sirer] Announcements P4-Buffer Overflow is
More informationSilberschatz and Galvin Chapter 12
Silberschatz and Galvin Chapter 12 I/O Systems CPSC 410--Richard Furuta 3/19/99 1 Topic overview I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O requests to hardware operations
More informationECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions
ECE332, Week 8 October 15, 2007 1 Topics Exceptions Hardware Interrupts Software exceptions Unimplemented instructions Software traps Other exceptions 2 1 Exception An exception is a transfer of control
More information[08] IO SUBSYSTEM 1. 1
[08] IO SUBSYSTEM 1. 1 OUTLINE Input/Output (IO) Hardware Device Classes OS Interfaces Performing IO Polled Mode Interrupt Driven Blocking vs Non-blocking Handling IO Buffering & Strategies Other Issues
More informationInterrupts in Zynq Systems
Interrupts in Zynq Systems C r i s t i a n S i s t e r n a U n i v e r s i d a d N a c i o n a l d e S a n J u a n A r g e n t i n a Exception / Interrupt Special condition that requires a processor's
More informationChapter 12: I/O Systems
Chapter 12: I/O Systems Chapter 12: I/O Systems I/O Hardware! Application I/O Interface! Kernel I/O Subsystem! Transforming I/O Requests to Hardware Operations! STREAMS! Performance! Silberschatz, Galvin
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations STREAMS Performance Silberschatz, Galvin and
More informationChapter 12: I/O Systems. Operating System Concepts Essentials 8 th Edition
Chapter 12: I/O Systems Silberschatz, Galvin and Gagne 2011 Chapter 12: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations STREAMS
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance Objectives Explore the structure of an operating
More informationWhat s An OS? Cyclic Executive. Interrupts. Advantages Simple implementation Low overhead Very predictable
What s An OS? Provides environment for executing programs Process abstraction for multitasking/concurrency scheduling Hardware abstraction layer (device drivers) File systems Communication Do we need an
More informationInterrupt/Timer/DMA 1
Interrupt/Timer/DMA 1 Exception An exception is any condition that needs to halt normal execution of the instructions Examples - Reset - HWI - SWI 2 Interrupt Hardware interrupt Software interrupt Trap
More informationTHE CPU SPENDS ALMOST ALL of its time fetching instructions from memory
THE CPU SPENDS ALMOST ALL of its time fetching instructions from memory and executing them. However, the CPU and main memory are only two out of many components in a real computer system. A complete system
More informationI/O Systems. Amir H. Payberah. Amirkabir University of Technology (Tehran Polytechnic)
I/O Systems Amir H. Payberah amir@sics.se Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) I/O Systems 1393/9/15 1 / 57 Motivation Amir H. Payberah (Tehran
More informationSingle thread Scheduler All processes called once each sample
Single thread Scheduler All processes called once each sample void main(void) { init_routines(); done = 0; while (!done) { perform_process1(); // Highest priority process perform_process2(); perform_process3();//
More informationChapter 3 - Top Level View of Computer Function
Chapter 3 - Top Level View of Computer Function Luis Tarrataca luis.tarrataca@gmail.com CEFET-RJ L. Tarrataca Chapter 3 - Top Level View 1 / 127 Table of Contents I 1 Introduction 2 Computer Components
More informationOPERATING SYSTEM. Chapter 9: Virtual Memory
OPERATING SYSTEM Chapter 9: Virtual Memory Chapter 9: Virtual Memory Background Demand Paging Copy-on-Write Page Replacement Allocation of Frames Thrashing Memory-Mapped Files Allocating Kernel Memory
More informationMemory management. Requirements. Relocation: program loading. Terms. Relocation. Protection. Sharing. Logical organization. Physical organization
Requirements Relocation Memory management ability to change process image position Protection ability to avoid unwanted memory accesses Sharing ability to share memory portions among processes Logical
More informationfor Operating Systems Computer Systems Laboratory Sungkyunkwan University
Architectural t Support for Operating Systems Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics Basic computer system architecture
More informationInterfacing. Introduction. Introduction Addressing Interrupt DMA Arbitration Advanced communication architectures. Vahid, Givargis
Interfacing Introduction Addressing Interrupt DMA Arbitration Advanced communication architectures Vahid, Givargis Introduction Embedded system functionality aspects Processing Transformation of data Implemented
More informationProcess Context & Interrupts. New process can mess up information in old process. (i.e. what if they both use the same register?)
1 Process Context 1.1 What is context? A process is sometimes called a task, subroutine or program. Process context is all the information that the process needs to keep track of its state. Registers Temporary
More informationReal-Time Programming
Real-Time Programming Week 7: Real-Time Operating Systems Instructors Tony Montiel & Ken Arnold rtp@hte.com 4/1/2003 Co Montiel 1 Objectives o Introduction to RTOS o Event Driven Systems o Synchronization
More informationTopics. Interfacing chips
8086 Interfacing ICs 2 Topics Interfacing chips Programmable Communication Interface PCI (8251) Programmable Interval Timer (8253) Programmable Peripheral Interfacing - PPI (8255) Programmable DMA controller
More informationI/O AND DEVICE HANDLING Operating Systems Design Euiseong Seo
I/O AND DEVICE HANDLING 2016 Operating Systems Design Euiseong Seo (euiseong@skku.edu) I/O Hardware Incredible variety of I/O devices Common concepts Port Bus (daisy chain or shared direct access) Controller
More informationCSCE Introduction to Computer Systems Spring 2019
CSCE 313-200 Introduction to Computer Systems Spring 2019 Processes Dmitri Loguinov Texas A&M University January 24, 2019 1 Chapter 3: Roadmap 3.1 What is a process? 3.2 Process states 3.3 Process description
More information4) In response to the the 8259A sets the highest priority ISR, bit and reset the corresponding IRR bit. The 8259A also places
Lecture-52 Interrupt sequence: The powerful features of the 8259A in a system are its programmability and the interrupt routine address capability. It allows direct or indirect jumping to the specific
More informationChapter 8 & Chapter 9 Main Memory & Virtual Memory
Chapter 8 & Chapter 9 Main Memory & Virtual Memory 1. Various ways of organizing memory hardware. 2. Memory-management techniques: 1. Paging 2. Segmentation. Introduction Memory consists of a large array
More informationGrundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss
Grundlagen Microcontroller Interrupts Günther Gridling Bettina Weiss 1 Interrupts Lecture Overview Definition Sources ISR Priorities & Nesting 2 Definition Interrupt: reaction to (asynchronous) external
More informationThe K Project. Interrupt and Exception Handling. LSE Team. May 14, 2018 EPITA. The K Project. LSE Team. Introduction. Interrupt Descriptor Table
and Exception Handling EPITA May 14, 2018 (EPITA) May 14, 2018 1 / 37 and Exception Handling Exception : Synchronous with program execution (e.g. division by zero, accessing an invalid address) : Asynchronous
More informationUNIT V INPUT OUTPUT ORGANIZATION
UNIT V Unit objective INPUT OUTPUT ORGANIZATION In this unit you will be introduced to : How program-controlled I/O is performed using polling, The idea of interrupts and the hardware and software needed
More informationLecture 4: Mechanism of process execution. Mythili Vutukuru IIT Bombay
Lecture 4: Mechanism of process execution Mythili Vutukuru IIT Bombay Low-level mechanisms How does the OS run a process? How does it handle a system call? How does it context switch from one process to
More informationFor more notes of DAE
Created by ARSLAN AHMED SHAAD ( 1163135 ) AND MUHMMAD BILAL ( 1163122 ) VISIT : www.vbforstudent.com Also visit : www.techo786.wordpress.com For more notes of DAE CHAPTER # 8 INTERRUPTS COURSE OUTLINE
More informationWhy use an Operating System? Operating System Definition
Why use an Operating System? Operating System Definition Provides a set of services to system users (collection of service programs) Shield between the user and the hardware Resource manager: CPU(s) memory
More informationComputer Architecture 5.1. Computer Architecture. 5.2 Vector Address: Interrupt sources (IS) such as I/O, Timer 5.3. Computer Architecture
License: http://creativecommons.org/licenses/by-nc-nd/3./ Hardware interrupt: 5. If in an eternal device (for eample I/O interface) a predefined event occurs this device issues an interrupt request to
More informationINPUT/OUTPUT ORGANIZATION
INPUT/OUTPUT ORGANIZATION Accessing I/O Devices I/O interface Input/output mechanism Memory-mapped I/O Programmed I/O Interrupts Direct Memory Access Buses Synchronous Bus Asynchronous Bus I/O in CO and
More informationChapter 13: I/O Systems
Chapter 13: I/O Systems Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance 13.2 Silberschatz, Galvin
More informationChapter 13: I/O Systems. Chapter 13: I/O Systems. Objectives. I/O Hardware. A Typical PC Bus Structure. Device I/O Port Locations on PCs (partial)
Chapter 13: I/O Systems Chapter 13: I/O Systems I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations Streams Performance 13.2 Silberschatz, Galvin
More informationComputer System Overview. Chapter 1
Computer System Overview Chapter 1 Operating System Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices Basic Elements
More informationEmbedded Software TI2726 B. 4. Interrupts. Koen Langendoen. Embedded Software Group
Embedded Software 4. Interrupts TI2726 B Koen Langendoen Embedded Software Group What is an Interrupt? Asynchronous signal from hardware Synchronous signal from software Indicates the need for attention
More informationINPUT/OUTPUT ORGANIZATION
INPUT/OUTPUT ORGANIZATION Accessing I/O Devices I/O interface Input/output mechanism Memory-mapped I/O Programmed I/O Interrupts Direct Memory Access Buses Synchronous Bus Asynchronous Bus I/O in CO and
More informationDesign and Implementation Interrupt Mechanism
Design and Implementation Interrupt Mechanism 1 Module Overview Study processor interruption; Design and implement of an interrupt mechanism which responds to interrupts from timer and UART; Program interrupt
More information1 PROCESSES PROCESS CONCEPT The Process Process State Process Control Block 5
Process Management A process can be thought of as a program in execution. A process will need certain resources such as CPU time, memory, files, and I/O devices to accomplish its task. These resources
More information