What do we have so far? Multi-Cycle Datapath (Textbook Version)
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1 What do we have so far? ulti-cycle Datapath (Textbook Version) CPI: R-Type = 4, Load = 5, Store 4, Branch = 3 Only one instruction being processed in datapath How to lower CPI further? #1 Lec # 8 Summer
2 Operations In Each Cycle R-Type Logic Immediate Load Store Branch IF Fetch IR em[pc] PC PC + 4 IR em[pc] PC PC + 4 IR em[pc] PC PC + 4 IR em[pc] PC PC + 4 IR em[pc] PC PC + 4 ID Decode A R[rs] B R[rt] ALUout PC + (SignExt(imm16) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm16) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm16) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm16) x4) A B R[rs] R[rt] ALUout PC + (SignExt(imm16) x4) EX Execution ALUout A + B ALUout A OR ZeroExt[imm16] ALUout A + SignEx(Im16) ALUout A + SignEx(Im16) If Equal = 1 PC ALUout E emory em[aluout] em[aluout] B WB Write Back R[rd] ALUout R[rt] ALUout R[rd] em #2 Lec # 8 Summer
3 Finite State achine (FS) Specification IR E[PC] PC PC instruction fetch A R[rs] B R[rt] ALUout PC +SX 0001 decode Execute R-type ALUout A fun B 0100 ORi ALUout A op ZX 0110 LW ALUout A + SX 1000 SW ALUout A + SX 1011 BEQ If A = B then PC ALUout 0010 emory R[rd] ALUout 0101 To instruction fetch R[rt] ALUout 0111 E[ALUout] 1001 R[rt] 1010 To instruction fetch E[ALUout] B 1100 To instruction fetch #3 Lec # 8 Summer Write-back
4 ulti-cycle Datapath (Our Version) npc_sel Next PC PC Fetch IR File Operand Fetch A B ExtOp ALUSrc ALUctr Ext ALU R emrd emwr em Access emto Data em Dst Wr. File isters added: IR: register A, B: Two registers to hold operands read from register file. R: or ALUOut, holds the output of the ALU : or emory data register (DR) to hold data read from data memory Result Store Equal #4 Lec # 8 Summer
5 Operations In Each Cycle R-Type Logic Immediate Load Store Branch IF Fetch IR em[pc] IR em[pc] IR em[pc] IR em[pc] IR em[pc] ID Decode A R[rs] B R[rt] A R[rs] A R[rs] A R[rs] B R[rt] A R[rs] B R[rt] If Equal = 1 EX Execution R A + B R A OR ZeroExt[imm16] R A + SignEx(Im16) R A + SignEx(Im16) PC PC (SignExt(imm16) x4) else PC PC + 4 E emory em[r] em[r] B PC PC + 4 WB Write Back R[rd] R PC PC + 4 R[rt] R PC PC + 4 R[rd] PC PC + 4 #5 Lec # 8 Summer
6 ulti-cycle Datapath CPI R-Type/Immediate: Require four cycles, CPI =4 IF, ID, EX, WB Loads: Require five cycles, CPI = 5 IF, ID, EX, E, WB Stores: Require four cycles, CPI = 4 IF, ID, EX, E Branches: Require three cycles, CPI = 3 IF, ID, EX Average program 3 CPI 5 depending on program profile (instruction mix). #6 Lec # 8 Summer
7 IPS ulti-cycle Datapath Performance Evaluation What is the average CPI? State diagram gives CPI for each instruction type. Workload (program) below gives frequency of each type. Type CPI i for type Frequency CPI i x freqi i Arith/Logic 4 40% 1.6 Load 5 30% 1.5 Store 4 10% 0.4 branch 3 20% 0.6 Average CPI: 4.1 Better than CPI = 5 if all instructions took the same number of clock cycles (5). #7 Lec # 8 Summer
8 Pipelining pipelining is a CPU implementation technique where multiple operations on a number of instructions are overlapped. The next instruction is fetched in the next cycle without waiting for the current instruction to complete. An instruction execution pipeline involves a number of steps, where each step completes one part of an instruction. Each step is called a pipeline stage or a pipeline segment. The stages or steps are connected one to the next to form a pipeline -- instructions enter at one end and progress through the stages and exit at the other end when completed. Pipeline Throughput : The instruction completion rate of the pipeline and is determined by how often an instruction exists the pipeline. The time to move an instruction one step down the line is is equal to the machine cycle and is determined by the stage with the longest processing delay. Pipeline Latency: The time required to complete an instruction: Cycle time x Number of pipeline stages. #8 Lec # 8 Summer
9 Single Cycle Vs. Pipelining P rogram e xecution Tim e o rder (in instructions) lw $ 1, 10 0($0 ) fetch ALU Data access Single Cycle lw $ 2, 20 0($0 ) 8 ns fetch ALU Data access lw $ 3, 30 0($0 ) Time for 1000 instructions = 8 x 1000 = 8000 ns 8 n s fetch 8 ns... Prog ram execution Time ord er (in instructions) lw $1, 1 00($0) lw $2, 2 00($0) fetch 2 ns fetch ALU Data access ALU Data access 5 Stage Pipeline lw $3, 3 00($0) 2 ns fetch ALU Data access 2 ns 2 n s 2 ns 2 ns 2 n s Time for 1000 instructions = time to fill pipeline + cycle time x 1000 = x 1000 = 2008 ns Pipelining Speedup = 8000/2008 = 3.98 #9 Lec # 8 Summer
10 Pipelining: Design Goals The length of the machine clock cycle is determined by the time required for the slowest pipeline stage. An important pipeline design consideration is to balance the length of each pipeline stage. If all stages are perfectly balanced, then the time per instruction on a pipelined machine (assuming ideal conditions with no stalls): Time per instruction on unpipelined machine Number of pipe stages Under these ideal conditions: Speedup from pipelining = the number of pipeline stages = k One instruction is completed every cycle: CPI = 1. #10 Lec # 8 Summer
11 From IPS ulti-cycle Datapath: Five Stages of Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load IF ID EX E WB 1- Fetch (IF) Fetch Fetch the instruction from the emory. 2- Decode (ID): isters Fetch and Decode. 3- Execute (EX): Calculate the memory address. 4- emory (E): Read the data from the Data emory. 5- Write Back (WB): Write the data back to the register file. #11 Lec # 8 Summer
12 Pipelined Processing Representation Clock cycle Number Time in clock cycles Number I IF ID EX E WB I+1 IF ID EX E WB I+2 IF ID EX E WB I+3 IF ID EX E WB I +4 IF ID EX E WB Time to fill the pipeline Pipeline Stages: IF = Fetch ID = Decode EX = Execution E = emory Access WB = Write Back First instruction, I Completed Last instruction, I+4 completed #12 Lec # 8 Summer
13 Pipelined Processing Time IF ID EX E WB Representation IF ID EX E WB IF ID EX E WB IF ID EX E WB Program Flow IF ID EX E WB IF ID EX E WB #13 Lec # 8 Summer
14 Clk Single Cycle, ulti-cycle, Vs. Pipeline Single Cycle Implementation: Cycle 1 Cycle 2 8 ns Load Store Waste 2ns Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk ultiple Cycle Implementation: Load IF ID EX E WB Store IF ID EX E R-type IF Pipeline Implementation: Load IF ID EX E WB Store IF ID EX E WB R-type IF ID EX E WB #14 Lec # 8 Summer
15 Single Cycle, ulti-cycle, Pipeline: Performance Comparison Example For 1000 instructions, execution time: Single Cycle achine: 8 ns/cycle x 1 CPI x 1000 inst = 8000 ns ulti-cycle achine: 2 ns/cycle x 4.6 CPI (due to inst mix) x 1000 inst = 9200 ns Ideal pipelined machine, 5-stages: 2 ns/cycle x (1 CPI x 1000 inst + 4 cycle fill) = 2008 ns #15 Lec # 8 Summer
16 Basic Pipelined CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select required datapath components and connections. 3. Assemble an initial datapath meeting the ISA requirements. 4. Identify pipeline stages based on operation, balancing stage delays, and ensuring no hardware conflicts exist when common hardware is used by two or more stages simultaneously in the same cycle. 5. Divide the datapath into the stages identified above by adding buffers between the stages of sufficient width to hold: fields. Remaining control lines needed for remaining pipeline stages. All results produced by a stage and any unused results of previous stages. 6. Analyze implementation of each instruction to determine setting of control points that effects the register transfer taking pipeline hazard conditions into account. 7. Assemble the control logic. #16 Lec # 8 Summer
17 IPS Pipeline Stage Identification IF: fetch ux 0 ID: decode/ register file read EX: Execute/ address calculation E: emory access WB: Write back 1 Add 4 Shift left 2 Add result Add PC Address memory Read register 1 Read Read data 1 register 2 isters Read data 2 Write register Write data 16 Sign extend 32 0 ux 1 Zero ALU ALU result Address Write data Data memory Read data ux 1 0 What is needed to divide datapath into pipeline stages? #17 Lec # 8 Summer
18 IPS: An Initial Pipelined Datapath 0 u x 1 Buffers between pipeline stages are added IF/ID ID/EX EX/E E/WB Add 4 Shift left 2 Add Add result PC Address memory Read register 1 Read data 1 Read register 2 isters Read data 2 Write register Write data 0 ux 1 Zero ALU ALU result Address Write data Data memory Read data 1 ux 0 16 Sign extend 32 IF ID EX E WB Fetch Decode Execution emory Write Back Can you find a problem even if there are no dependencies? What instructions can we execute to manifest the problem? #18 Lec # 8 Summer
19 A Corrected Pipelined Datapath 0 u x 1 IF/ID ID/EX EX/E E/WB Add 4 Shift left 2 Add result Add PC Address memory Read register 1 Read data 1 Read register 2 isters Read data 2 Write register Write data 0 ux 1 Zero ALU ALU result Address Write data Data memory Read data 1 ux 0 16 Sign extend 32 IF ID EX E WB Fetch Decode Execution emory Write Back #19 Lec # 8 Summer
20 Representing Pipelines Graphically Time (in clock cycles) Program execution order (in instructions) lw $10, 20($1) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 I ALU D sub $11, $2, $3 I ALU D Can help with answering questions like: How many cycles does it take to execute this code? What is the ALU doing during cycle 4? Use this representation to help understand datapaths #20 Lec # 8 Summer
21 Adding Pipeline Control Points PCSrc 0 u x 1 IF/ID ID/EX EX/E E/WB Add 4 Write Shift left 2 Add Add result Branch PC Address memory Read register 1 Read Read data 1 register 2 isters Read Write data 2 register Write data ALUSrc 0 u x 1 Zero ALU ALU result Address Write emwrite Data memory Read data emto 1 u x 0 [15 0] 16 Sign 32 extend 6 ALU control data emread [20 16] [15 11] 0 u x 1 ALUOp Dst #21 Lec # 8 Summer
22 Pipeline Control Pass needed control signals along from one stage to the next as the instruction travels through the pipeline just like the data Execution/Address Calculation stage control lines emory access stage control lines Write-back stage control lines Dst ALU Op1 ALU Op0 ALU Src Branch em Read em Write write em to R-format lw sw X X beq X X WB Control WB EX WB IF/ID ID/EX EX/E E/WB #22 Lec # 8 Summer
23 Pipeline Control The ain Control generates the control signals during /Dec Control signals for Exec (ExtOp, ALUSrc,...) are used 1 cycle later Control signals for em (emwr Branch) are used 2 cycles later Control signals for Wr (emto emwr) are used 3 cycles later ID EX em WB ExtOp ExtOp ALUSrc ALUSrc IF/ID ister ain Control ALUOp Dst emwr Branch emto ID/Ex ister ALUOp Dst emwr Branch emto Ex/em ister emwr Branch emto em/wb ister emto Wr Wr Wr Wr #23 Lec # 8 Summer
24 Pipelined Datapath with Control Added PCSrc 0 u x 1 Control ID/EX WB EX/E WB E/WB IF/ID EX WB Add PC 4 Address memory Read register 1 Read data 1 Read register 2 isters Read Write data 2 register Write data R egwrite Shift left 2 0 u x 1 Add Add result ALUSrc Zero ALU ALU result Branch Write data emwrite Address Data memory Read data emto 1 u x 0 [15 0] 16 Sign 32 extend 6 ALU control emread [20 16] [15 11] 0 u x 1 Dst ALUOp Target address of branch determined in E #24 Lec # 8 Summer
25 Basic Performance Issues In Pipelining Pipelining increases the CPU instruction throughput: The number of instructions completed per unit time. Under ideal condition instruction throughput is one instruction per machine cycle, or CPI = 1 Pipelining does not reduce the execution time of an individual instruction: The time needed to complete all processing steps of an instruction (also called instruction completion latency). It usually slightly increases the execution time of each instruction over unpipelined implementations due to the increased control overhead of the pipeline and pipeline stage registers delays. #25 Lec # 8 Summer
26 Pipelining Performance Example Example: For an unpipelined machine: Clock cycle = 10ns, 4 cycles for ALU operations and branches and 5 cycles for memory operations with instruction frequencies of 40%, 20% and 40%, respectively. If pipelining adds 1ns to the machine clock cycle then the speedup in instruction execution from pipelining is: Non-pipelined Average instruction execution time = Clock cycle x Average CPI = 10 ns x ((40% + 20%) x %x 5) = 10 ns x 4.4 = 44 ns In the pipelined five implementation five stages are used with an average instruction execution time of: 10 ns + 1 ns = 11 ns Speedup from pipelining = time unpipelined time pipelined = 44 ns / 11 ns = 4 times #26 Lec # 8 Summer
27 Pipeline Hazards Hazards are situations in pipelining which prevent the next instruction in the instruction stream from executing during the designated clock cycle resulting in one or more stall cycles. Hazards reduce the ideal speedup gained from pipelining and are classified into three classes: Structural hazards: Arise from hardware resource conflicts when the available hardware cannot support all possible combinations of instructions. Data hazards: Arise when an instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline. Control hazards: Arise from the pipelining of conditional branches and other instructions that change the PC. #27 Lec # 8 Summer
28 Structural Hazards In pipelined machines overlapped instruction execution requires pipelining of functional units and duplication of resources to allow all possible combinations of instructions in the pipeline. If a resource conflict arises due to a hardware resource being required by more than one instruction in a single cycle, and one or more such instructions cannot be accommodated, then a structural hazard has occurred, for example: when a machine has only one register file write port or when a pipelined machine has a shared single-memory pipeline for data and instructions. stall the pipeline for one cycle for register writes or memory data access #28 Lec # 8 Summer
29 Structural hazard Example: Single emory For s & Data Time (clock cycles) I n s t r. O r d e r Load Instr 1 Instr 2 Instr 3 Instr 4 ALU em em em em ALU em ALU em em ALU em ALU em em Detection is easy in this case (right half highlight means read, left half write) #29 Lec # 8 Summer
30 Data Hazards Example Problem with starting next instruction before first is finished Data dependencies here that go backward in time create data hazards. sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Time (in clock cycles) Value of register $2: Program execution order (in instructions) sub $2, $1, $3 CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 I CC 7 CC 8 CC / D and $12, $2, $5 I D or $13, $6, $2 I D add $14, $2, $2 I D sw $15, 100($2) I D #30 Lec # 8 Summer
31 Data Hazard Resolution: Stall Cycles Stall the pipeline by a number of cycles. The control unit must detect the need to insert stall cycles. In this case two stall cycles are needed. Time (in clock cycles) Value of register $2: Program execution order (in instructions) sub $2, $1, $3 CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 I CC 7 CC / D CC 9 20 CC CC and $12, $2, $5 I STALL STALL D or $13, $6, $2 STALL STALL I D add $14, $2, $2 I D sw $15, 100($2) I D #31 Lec # 8 Summer
32 Performance of Pipelines with Stalls Hazards in pipelines may make it necessary to stall the pipeline by one or more cycles and thus degrading performance from the ideal CPI of 1. CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction If pipelining overhead is ignored and we assume that the stages are perfectly balanced then: Speedup = CPI unpipelined / (1 + Pipeline stall cycles per instruction) When all instructions take the same number of cycles and is equal to the number of pipeline stages then: Speedup = Pipeline depth / (1 + Pipeline stall cycles per instruction) #32 Lec # 8 Summer
33 Data Hazard Resolution: Compiler Scheduling The compiler can guarantee that no data hazards exist by re-ordering instructions and/or adding NOP instructions where needed. For the previous example: sub $2, $1, $3 nop nop and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) #33 Lec # 8 Summer
34 Data Hazard Resolution: Forwarding Observation: Why not use temporary results produced by memory/alu and not wait for them to be written back in the register bank. Forwarding is a hardware-based technique (also called register bypassing or short-circuiting) used to eliminate or minimize data hazard stalls that makes use of this observation. Using forwarding hardware, the result of an instruction is copied directly from where it is produced (ALU, memory read port etc.), to where subsequent instructions need it (ALU input register, memory write port etc.) #34 Lec # 8 Summer
35 Data Hazard Resolution: Forwarding ister file forwarding to handle read/write to same register ALU forwarding #35 Lec # 8 Summer
36 Pipelined Datapath With Forwarding ID/EX WB EX/E Control WB E/WB IF/ID EX WB PC memory isters u x u x ALU Data memory u x IF/ID.isterRs Rs IF/ID.isterRt Rt IF/ID.isterRt IF/ID.isterRd Rt Rd u x EX/E.isterRd Forwarding unit E/WB.isterRd #36 Lec # 8 Summer
37 Data Hazard Example With Forwarding Value of register $2 : Value of EX/E : Value of E/WB : Time (in clock cycles) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC / X X X 20 X X X X X X X X X 20 X X X X Program execution order (in instructions) sub $2, $1, $3 I D and $12, $2, $5 I D or $13, $6, $2 I D add $14, $2, $2 I D sw $15, 100($2) I D #37 Lec # 8 Summer
38 A Data Hazard Requiring A Stall A load followed by an R-type instruction that uses the loaded value Program execution order (in instructions) lw $2, 20($1) Time (in clock cycles) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 I D CC 7 CC 8 CC 9 and $4, $2, $5 I D or $8, $2, $6 I D add $9, $4, $2 I D slt $1, $6, $7 I D Even with forwarding in place a stall cycle is needed This condition must be detected by hardware #38 Lec # 8 Summer
39 A Data Hazard Requiring A Stall A load followed by an R-type instruction that uses the loaded value Program execution order (in instructions) Time (in clock cycles) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 CC 10 lw $2, 20($1) I D and $4, $2, $5 I D or $8, $2, $6 add $9, $4, $2 I I D bubble I D slt $1, $6, $7 I D We can stall the pipeline by keeping an instruction in the same stage #39 Lec # 8 Summer
40 Compiler Scheduling Example Reorder the instructions to avoid as many pipeline stalls as possible: lw $15, 0($2) lw $16, 4($2) add $14, $5, $16 sw $16, 4($2) The data hazard occurs on register $16 between the second lw and the add resulting in a stall cycle With forwarding we need to find only one independent instructions to place between them, swapping the lw instructions works: lw $16, 4($2) lw $15, 0($2) add $14, $5, $16 sw $16, 4($2) Without forwarding we need two independent instructions to place between them, so in addition a nop is added. lw $16, 4($2) lw $15, 0($2) nop add $14, $5, $16 sw $16, 4($2) #40 Lec # 8 Summer
41 Datapath With Hazard Detection Unit A load followed by an instruction that uses the loaded value is detected and a stall cycle is inserted. Hazard detection unit ID/EX.emRead ID/EX IF/IDWrite IF/ID Control 0 ux WB EX EX/E WB E/WB WB PCWrite PC memory isters ux ALU Data memory ux ux IF/ID.isterRs IF/ID.isterRt IF/ID.isterRt IF/ID.isterRd Rt Rd ux EX/E.isterRd ID/EX.isterRt Rs Rt Forwarding unit E/WB.isterRd #41 Lec # 8 Summer
42 Control Hazards: Example Three other instructions are in the pipeline before branch instruction target decision is made when BEQ is in E stage. Program execution order (in instructions) Time (in clock cycles) CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9 40 beq $1, $3, 7 I D 44 and $12, $2, $5 I D 48 or $13, $6, $2 I D 52 add $14, $2, $2 I D 72 lw $4, 50($7) I D In the above diagram, we are predicting branch not taken Need to add hardware for flushing the three following instructions if we are wrong losing three cycles. #42 Lec # 8 Summer
43 Reducing Delay of Taken Branchs Next PC of a branch known in E stage: Costs three lost cycles if taken. If next PC is known in EX stage, one cycle is saved. Branch address calculation can be moved to ID stage using a register comparator, costing only one cycle if branch is taken. IF.Flush Hazard detection unit u x ID/EX WB EX/E Control 0 u x WB E/WB IF/ID EX WB PC 4 memory Shift left 2 isters = u x u x ALU Data memory u x Sign extend u x Forwarding unit #43 Lec # 8 Summer
44 Pipeline Performance Example Assume the following IPS instruction mix: Type Frequency Arith/Logic 40% Load 30% of which 25% are followed immediately by an instruction using the loaded value Store 10% branch 20% of which 45% are taken What is the resulting CPI for the pipelined IPS with forwarding and branch address calculation in ID stage? CPI = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + stalls by loads + stalls by branches = 1 +.3x.25x1 +.2 x.45x1 = = #44 Lec # 8 Summer
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