These 3 registers contain enable, priority,
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1 8.3.2) Registers Related to Interrupts These registers enable/disable the interrupts, set the priority of the interrupts, and record the status of each interrupt source. RCON INTCON, INTCON2, and INTCON3 PIR1, PIR2, and PIR3 PIE1, PIE2, and PIE3 IPR1, IPR2, and IPR3 Each interrupt source has three bits to control its operation: 1) A flag bit to indicate whether an interrupt event has occurred. 2) An enable bit enabling/disabling the interrupt source. 3) A priority bit selecting high or low priority, which has effect only when the priority scheme is enabled ) Reset Configuration Register (RCON) The RCON register has a bit (IPEN Interrupt Priority Enable bit) to enable interrupt priority scheme. The other bits are used to indicate the cause of reset. IP EN - - RI TO PD P OR BOR IPEN: Interrupt priority enable bit 0: Disable priority levels on interrupts 1: Enable priority levels on interrupts RI: RESET instruction flag bit 0: T he reset instruction was executed causing a device reset 1: T he reset instructionwas not executed TO: Watchdog timeout flag bit 0: A watchdog timeout occurred 1: After power-up, CLRWDT instruction, or SLEEP instruction PD: Power-down detection flag bit 0: By execution of the SLEEP instruction 1: After power up or by the CLRWDT instruction POR: Power-on reset status bit 0: A power-on reset has occurred 1: A power-on reset has not occurred BOR: Brown-out reset status bit (PIC18CX01 does not have this bit) 0: A brown-out reset has occurred 1: A brown-out reset has not occurred Figure 6.1 The RCON Register (reprint with permission of Microchip) ) Interrupt Control Registers (INTCON, INTCON2, INTCON3) These 3 registers contain enable, priority, and flag bits for external INT pins, port B pin change, and Timer 0 (TMR0) overflow interrupt. 30 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF GIE/GIEH: Global interrupt enable bit when IPEN (RCON<7>)= 0 0: disables all interrupts 1: enables all interrupts when IPEN = 1 0: disables all interrupts 1: enables all high priority interrupts PEIE/GEIEL: Peripheral interrupt enable bit when IPEN = 0: 0: disables all peripheral interrupts 1: enables all peripheral interrupts when IPEN = 1 0: disables all low priority interrupts 1: enables all low priority interrupts TMR0IE: TMR0 overflow interrupt enable bit 0: disables TMR0 overflow interrupt 1: enables TMR0 overflow interrupt INT0IE: INT0 pin interrupt enable 0: disables INT0 pin interrupt 1: enables INT0 pin interrupt RBIE: PORTB port change interrupt enable bit 0: disables PORTB port change interrupt 1: enables PORTB port change interrupt TMR0IF: TMR0 overflow interrupt flag bit 0: TMR0 has not overflowed 1: TMR0 has overflowed INT0IF: INT0 pin interrupt flag bit 0: the INT0 pin interrupt did not occur 1: the INT0 pin interrupt has occurred PORTB port change interrupt flag bit 0: none of the RB7:RB4 pins have changed state 1: at least one of the RB7:RB4 pins change state Figure 6.2a The INTCON register (reprint with permission of Microchip) RBIF 31 Lecturer: Dr Jamaludin Bin Omar 8-1
2 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP RBPU: PORTB pull-up enable bit 0: all PORTB pull-ups are enabled 1: all PORTB pull-ups are disabled INTEDG0..INTEDG3: INT0..INT3 interrupt pins edge select 0: interrupt on falling edge 1: interrupt on rising edge TMR0IP: TMR0 overflow interrupt priority bit INT3IP: INT3 interrupt priority bit (not available in P18FXX8 & P18CX01) RBIP: PORTB change interrupt priority bit Note. 1. PIC18FXX8 does not have INTEDG2 & INTEDG3) 2. PIC18C601/801 does not have INTEDG3 Figure 6.2b The INTCON2 register (reprint with permission of Microchip) 32 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF INT2IP..INT1IP: INT2..INT1 interrupt priority bit INT3IE..INT1IE: INT3..INT1 interrupt enable bit 0: disable interrupt 1: enable interrupt INT3IF..INT1IF: INT3..INT1 interrupt flag bit 0: interrupt did not occur 1: interrupt occurred Note. 1. PIC18FXX2, PIC18CXX2, PIC18CXX8, and PIC18FXX8 do not have INT2 and INT3 enable and flag bits 2. PIC18C601/801 does not have INT3 enable and flag bits Figure 6.2c The INTCON3 register (reprint with permission of Microchip) ) PIC18 Interrupt Operation 8.4) PIC18 Interrupt Operation (Cont) The interrupt priority scheme can be enabled (IPEN=1) or disabled (IPEN=0). When IPEN=1, all interrupts are divided into core group and peripheral group. The priority bits of the interrupts sources in the core group are contained in one of the interrupt control registers (INTCON, INTCON2, and INTCON3). When the priority scheme is enabled, all highpriority interrupts are under the control of a twolevel interrupt enabling mechanism. All low-priority interrupts are under the control of a three-level interrupt enabling scheme. 49 When the priority scheme is disabled, all interrupts in the core group are under the control of a two-level interrupt enabling scheme. All interrupts in the peripheral group are under the control of a three-level enabling scheme. The following interrupts are in the core group: 1) INT3 INT0 pin interrupts (RB3 RB0) 2) TMR0 overflow interrupt 3) PORTB input pin (RB7 RB4) change interrupts 50 Lecturer: Dr Jamaludin Bin Omar 8-2
3 8.4.1) PIC18 Interrupt Without Setting Priority The priority scheme is disabled by clearing the bit 7 of the RCON register, i.e. IPEN is logic 0. All interrupt sources share the common interrupt vector at 0x In order to identify the cause of interrupt, one need to check each individual interrupt flag bit. The interrupt sources in the core group can be enabled by setting the GIE bit and the corresponding enable bit of the interrupt source. For example, to enable TMR0 interrupt one must set both the GIE and the TMR0IE bits. The interrupts in the peripheral group can be enabled by setting the GIE, PEIE, and the associated interrupt enable bits. For example, to enable A/D conversioncomplete interrupt one needs to set the GIE, PEIE, and the ADIE bits ) PIC18 Interrupt Without Setting Priority (Cont) When an interrupt is responded to (being serviced), the GIE bit is cleared to disable further interrupt. The return address is pushed onto return address stack and the PC is loaded with the interrupt vector. Most interrupt flags must be cleared by the software in ISR to avoid repetitive interrupts from same source. The last instruction of an ISR must be instruction. The execution of this instruction will cause the top word of the hardware stack to be popped into the PC and the GIE bit to be set. After this, program control is returned to the interrupted program, and interrupt is re-enabled. This instruction has the option to restore the WREG, the STATUS, and the BSR registers from the fast register stack if the application requires it ) PIC18 Interrupt With Priority Enabled 8.4.3) PIC18 Interrupts in the Core Group Should be used when certain interrupts need to be serviced promptly. The PEIE bit of the INTCON register is used as the lowpriority interrupt enable bit. A high-priority interrupt is enabled when the GIEH bit and its interrupt enable bit are set to 1. By default, all interrupts are placed in high-priority level after reset. The interrupt vector is at 0x A low-priority interrupt is enabled when the GIEH, GIEL, and its associated interrupt enable bits are all set to 1. The interrupt vector is at 0x Pending interrupts in the high-priority group will always be served before the interrupts in the low-priority group. Interrupt flags must be cleared in the interrupt service routine to avoid recursive interrupts ) INT0 INT3 Pin Interrupts All INT pins interrupt (INT0 INT3) are edgetriggered. The edge-select bits are contained in the INTCON2 register. When an edge-select bit is set to 1, the corresponding INT pin interrupt on the rising edge. 54 Lecturer: Dr Jamaludin Bin Omar 8-3
4 8.4.3) PIC18 Interrupt in the Core Group (Cont) 8.5) PIC18 Interrupt Programming ) Port B Pins Input Change Interrupt An input change on pins RB7 RB4 sets the flag bit RBIF (INTCON<0>). If the RBIE bit is set, then the setting of the RBIF bit causes an interrupt. In order to use this interrupt, the RB7 RB4 pins must be configured for input. Two steps are needed: Step 1 Write the interrupt service routine and place it in the predefined program memory. Step 2 Set the appropriate interrupt enable bits to enable the desired interrupt. Reading the PORTB port will clear the RBIF flag bit ) Interrupt Programming in Assembly Language #1 Example 6.1: Circuit is as shown in Figure 6.6. Write a main program and an INT0 interrupt service routine in assembly language. The main program initializes a counter to 0, enables the INT0 interrupt, and then stays in a while-loop to wait forever. The INT0 ISR simply increments the counter by 1 and outputs it to the LEDs. Whenever the count is incremented to 15, ISR resets it to 0. #include <p18f8720.inc> count set 0x00 ; count value to be output to LEDs 0x00 main 0x08 ; INT interrupt vector int0_isr 0x18 ; pseudo interrupt service routine Lecturer: Dr Jamaludin Bin Omar 8-4
5 ; main main program: initialize and wait for the interrupt main clrf count,a ; initialize the count to 0 movlw 0xF0 ; configure port D lower movwf TRISD ; 4 pins for output movff count,portd ; output count to port D bsf RCON,IPEN,A ; enable priority interrupt bcf INTCON,INT0IF ; clear INT0 flag movlw 0x90 ; set INT0 interrupt to high priority movwf INTCON,A ; enable INT0 interrupt forever forever ; wait for the interrupt ; INT0 pin interrupt service routine int0_isr bcf INTCON,INT0IF ; clear INT0 interrupt flag bit movlw 0x0F cpfseq count,a ; count equal to 15 already? add_1 clrf count,a ; reset count to 0 after reaching 15 update add_1 incf count,f,a update movff count,portd ; output the count to LEDs end 61 Int0 DEMO ) Interrupt Programming in Assembly Language # ) Interrupt Programming in Assembly Language #2 (Cont) Example 6.2: Suppose port D pins RD3..RD0 are driving four LEDS. Write an assembly program that chooses the instruction clock as the clock source for Timer 1 and set the prescale factor so that it overflows twice every second. The program will increment a counter by one in every Timer 1 overflow interrupt and output the count value to LEDs. Program the Timer 1 interrupt to the low-priority group. Assume that the crystal oscillator used in the demo board is 40 MHz. #include <p18f452.inc> led_cnt set 0x00 0x00 start 0x08 0x18 ; Low priority group tmr1_isr ; jump to Timer 1 ISR Lecturer: Dr Jamaludin Bin Omar 8-5
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