Using XAP Processors in Space Applications

Size: px
Start display at page:

Download "Using XAP Processors in Space Applications"

Transcription

1 Using XAP Processors in Space Applications MESA Roundtable: ESTEC, 4 November 21 Chris Roberts and Alistair Morfey 8 November 21 ASICs-P-78 v1.2

2 Introduction to Cambridge Consultants Challenges for Processors in Space Introduction to XAP Processors XAP in Space applications Applications 2 8 November 21 ASICs-P-78 v1.2

3 Cambridge Consultants a multi-disciplinary engineering and design consultancy. Established out of Cambridge University in staff in Cambridge UK, 4 in Boston MA We design and develop innovative products, processes and systems using multiskilled teams supported with in-house services, labs and prototyping capabilities Our work is typically on strategic projects that require deep technical and market knowledge We serve a worldwide client base ranging from funded start-ups to blue chips working in: Semiconductors, processors Aerospace, transport, defence Energy, metering, security Healthcare, industrial, manufacturing, retail Communications, wireless, consumer 3 8 November 21 ASICs-P-78 v1.2

4 Introduction to Cambridge Consultants Challenges for Processors in Space Introduction to XAP Processors XAP in Space applications Applications 4 8 November 21 ASICs-P-78 v1.2

5 What are the problems with using a processor in space? Low power Long lifetimes Low area to permit redundancy High reliability Radiation environment Need protection from Single Event Upset (SEU) and other damage Particularly in the memory, as this is often the larger area Ability to safely perform (large) software upgrades and (small) patches while in orbit Large audience with a big range of technical requirements Both high level and low level software should be supported Use cases in FPGA, custom ASIC or standard microcontroller 5 8 November 21 ASICs-P-78 v1.2

6 Introduction to Cambridge Consultants Challenges for Processors in Space Introduction to XAP Processors XAP in Space Applications 6 8 November 21 ASICs-P-78 v1.2

7 XAPs are a family of 16 bit processors optimised for low power, small silicon area and easy verification XAPs have been sold since there are now over 1 billion XAPs in silicon There is probably a XAP in your pocket already! XAP is used in most Bluetooth chips for mobile phones and headsets XAP and xide (Bluelab) are recognised success factors for CSR s business Ember Communications has XAP in the EM25 and EM26 ZigBee chips 3M uses XAP in its range of touch screen controllers Other licensees used XAP in their ASICs or ASSPs Including high-reliability applications such as in-body medical products 7 8 November 21 ASICs-P-78 v1.2

8 Latest XAP 16-bit processors XAP4 and XAP5 XAP4 XAP5 12k gates Up to 64kB memory 18k gates Up to 16MB memory Modern RISC Von Neumann processors Non-invasive debug: xsif (external serial) isif (internal parallel) GNU compile chain (GCC and Binutils) C, Ada, (C++ soon). User and privileged modes enable code separation Nested Interrupts and Exceptions (error-handling) 2 Stack Pointers. Typical usage : SP for a single persistent system stack SP1 for multiple task stacks ASIC xap5_system xap5 single xsif xap5 clu xap5 ivc xap5 mmu IO registers RAM ROM 8 8 November 21 ASICs-P-78 v1.2

9 XAP5 hardware Example shown is XAP5 Delivered to licensees as Verilog RTL ASIC or FPGA Fully static design supports clock stopping or frequency changes xsif xap5_system irq With test benches, synthesis scripts, documents and tools isif irq_num[4:] priority[3:] xap5_ivc interrupt[31:] xap5_single is fixed xap5_ivc and xap5_mmu are customised per application Both minimal and fully featured templates for the IVC and MMU are provided xap5_clu is added to execute Custom Logic Unit instructions if needed. No change to tool chain needed clk resetb_sif resetb_xap force_stop xap5_single xap5_clu logical_address[23:] program_counter[23:] ivc_cs ivc_data_read[15:] xap5_mmu data_write[15:] address[23:] ioreg_cs ioreg_data_read[15:] ram_cs ram_data_read[15:] IO regs RAM XAP5 supports 32 interrupts (4 NMI and 28 maskable) and 32 exceptions wake_up data_read[15:] rom_cs rom_data_read[15:] we we_bit byte[1:] ROM Unified data and address bus Von Neumann design 9 8 November 21 ASICs-P-78 v1.2

10 XAP5 programmer s model Normal Registers Address Registers Special Registers Breakpoint Registers 23 R R1 R2 R3 R4 R5 R6 MESA Roundtable, R7 ESTEC, Near/Far 4 November mode 21 Program Counter PC Stack Pointer SP Current Vector Pointer [23:8] Read only 15 BRK BRK1 BRK2 BRK3 FLAGS INFO BRKE x F Return Value, Function Argument Function Argument 1 Function Argument 2 Function Argument 3 P 3 15 SP P 2 E 3 P 1 R 3 P S 4 S 3 W 3 E 2 S 2 R 2 S 1 S I M 1 S R R N L W 2 E 1 R 1 M W 1 SP1 V C N Z K 1 E R K W %r %r1 %r2 %r3 %r4 %r5 %r6 %r7 %pc %sp %sp %sp1 %vp %flags %info %brke %brk %brk1 %brk2 %brk3 1 8 November 21 ASICs-P-78 v1.2

11 XAP tools xide and GCC / binutils Download from Leverages investment in GNU compilers and tool chain Compilers for C and ADA (C++ soon) Achieves very high code density World class verification and debug tools xide provides: an extensible instruction set software simulator Real time hardware interface to target device Tools use the published xsif API for non-invasive debug xide SIF Explorer Python scripts Custom applications (e.g. LabView, Matlab, C, C++, python) 11 8 November 21 ASICs-P-78 v1.2

12 Introduction to Cambridge Consultants Challenges for Processors in Space Introduction to XAP Processors XAP in Space Applications 12 8 November 21 ASICs-P-78 v1.2

13 13 8 November 21 ASICs-P-78 v1.2

14 14 8 November 21 ASICs-P-78 v1.2

15 15 8 November 21 ASICs-P-78 v1.2

16 16 8 November 21 ASICs-P-78 v1.2

17 What features of XAP are most useful for space applications? Low power Few gates Small memories because of high code densities Flexible memory interface Customisable interrupts, exceptions and instructions Easy restore of state Non-invasive debug State of the art tools Rich, dense, regular instruction set Can be used in ASICs and FPGAs 17 8 November 21 ASICs-P-78 v1.2

18 Contact details: Cambridge Consultants Ltd Cambridge Consultants Inc Science Park, Milton Road 11 Main Street Cambridge, CB4 DW Cambridge MA 2142 England USA Tel: +44() Tel: Fax: +44() Fax: Registered No England Cambridge Consultants is part of the Altran group, the European leader in Innovation Consulting. Commercially Confidential This Presentation contains ideas and information which are proprietary to Cambridge Consultants Limited and/or Cambridge Consultants Inc: it is given to you in confidence. You are authorised to open and view any electronic copy we send you of this document within your organisation and to print a single copy. Otherwise the material may not in whole or in part be copied, stored electronically or communicated to third parties without the prior written agreement of Cambridge Consultants Limited and/or Cambridge Consultants Inc. 21 Cambridge Consultants Ltd, Cambridge Consultants Inc. All rights reserved November 21 ASICs-P-78 v1.2

_äìé`çêé» VM Memory Mapping and Memory Usage. Application Note. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom

_äìé`çêé» VM Memory Mapping and Memory Usage. Application Note. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom _äìé`çêé» VM Memory Mapping and Memory Usage Application Note November 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 4187346 Tel: +44 (0)1223 692000

More information

user guide January 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England

user guide January 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England user guide January 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 4187346 Tel: +44 (0)1223 692000 Fax: +44 (0)1223 692001 www.csr.com Contents Contents

More information

The ARM Cortex-M0 Processor Architecture Part-1

The ARM Cortex-M0 Processor Architecture Part-1 The ARM Cortex-M0 Processor Architecture Part-1 1 Module Syllabus ARM Architectures and Processors What is ARM Architecture ARM Processors Families ARM Cortex-M Series Family Cortex-M0 Processor ARM Processor

More information

ASYNC Rik van de Wiel COO Handshake Solutions

ASYNC Rik van de Wiel COO Handshake Solutions ASYNC 2006 Rik van de Wiel COO Handshake Solutions Outline Introduction to Handshake Solutions Applications Design Tools ARM996HS Academic Program Handshake Solutions Started as research project in Philips

More information

The Hidden Decisions Behind Covert Surveillance

The Hidden Decisions Behind Covert Surveillance The Hidden Decisions Behind Covert Surveillance The challenge of increased performance requirements with reduced power, size and weight Paste an image over the circle and use Send Backward tool 3 times

More information

V8-uRISC 8-bit RISC Microprocessor AllianceCORE Facts Core Specifics VAutomation, Inc. Supported Devices/Resources Remaining I/O CLBs

V8-uRISC 8-bit RISC Microprocessor AllianceCORE Facts Core Specifics VAutomation, Inc. Supported Devices/Resources Remaining I/O CLBs V8-uRISC 8-bit RISC Microprocessor February 8, 1998 Product Specification VAutomation, Inc. 20 Trafalgar Square Nashua, NH 03063 Phone: +1 603-882-2282 Fax: +1 603-882-1587 E-mail: sales@vautomation.com

More information

ARM Ltd. ! Founded in November 1990! Spun out of Acorn Computers

ARM Ltd. ! Founded in November 1990! Spun out of Acorn Computers ARM Architecture ARM Ltd! Founded in November 1990! Spun out of Acorn Computers! Designs the ARM range of RISC processor cores! Licenses ARM core designs to semiconductor partners who fabricate and sell

More information

ARM Processors for Embedded Applications

ARM Processors for Embedded Applications ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or

More information

FT-UNSHADES credits. UNiversity of Sevilla HArdware DEbugging System.

FT-UNSHADES credits. UNiversity of Sevilla HArdware DEbugging System. FT-UNSHADES Microelectronic Presentation Day February, 4th, 2004 J. Tombs & M.A. Aguirre jon@gte.esi.us.es, aguirre@gte.esi.us.es AICIA-GTE of The University of Sevilla (SPAIN) FT-UNSHADES credits UNiversity

More information

DQ8051. Revolutionary Quad-Pipelined Ultra High performance 8051 Microcontroller Core

DQ8051. Revolutionary Quad-Pipelined Ultra High performance 8051 Microcontroller Core DQ8051 Revolutionary Quad-Pipelined Ultra High performance 8051 Microcontroller Core COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was

More information

EEM870 Embedded System and Experiment Lecture 3: ARM Processor Architecture

EEM870 Embedded System and Experiment Lecture 3: ARM Processor Architecture EEM870 Embedded System and Experiment Lecture 3: ARM Processor Architecture Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw March 2014 Agenda

More information

Ten Reasons to Optimize a Processor

Ten Reasons to Optimize a Processor By Neil Robinson SoC designs today require application-specific logic that meets exacting design requirements, yet is flexible enough to adjust to evolving industry standards. Optimizing your processor

More information

Chapter 5. Introduction ARM Cortex series

Chapter 5. Introduction ARM Cortex series Chapter 5 Introduction ARM Cortex series 5.1 ARM Cortex series variants 5.2 ARM Cortex A series 5.3 ARM Cortex R series 5.4 ARM Cortex M series 5.5 Comparison of Cortex M series with 8/16 bit MCUs 51 5.1

More information

What do we expect from Wireless in the Factory?

What do we expect from Wireless in the Factory? What do we expect from Wireless in the Factory? And what are we doing about it? ETSI Wireless Factory Workshop, 15 December 2008 Tim Whittaker System Architect, Wireless Division 11 December 2008 S4989-P-188

More information

So you think developing an SoC needs to be complex or expensive? Think again

So you think developing an SoC needs to be complex or expensive? Think again So you think developing an SoC needs to be complex or expensive? Think again Phil Burr Senior product marketing manager CPU Group NMI - Silicon to Systems: Easy Access ASIC 23 November 2016 Innovation

More information

CAN on Integration Technologies

CAN on Integration Technologies CAN on Integration Technologies CAN technology has reached the mature state where the powerful network technology is well covered by standard parts; mainly processors with integrated CAN periphery. Nevertheless

More information

_äìé`çêé» UART Host Transport Summary. February 2004

_äìé`çêé» UART Host Transport Summary. February 2004 _äìé`çêé» UART Host Transport Summary February 2004 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 3665875 Tel: +44 (0)1223 692000 Fax: +44 (0)1223 692001

More information

DoCD IP Core. DCD on Chip Debug System v. 6.02

DoCD IP Core. DCD on Chip Debug System v. 6.02 2018 DoCD IP Core DCD on Chip Debug System v. 6.02 C O M P A N Y O V E R V I E W Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and

More information

Embedded System Design

Embedded System Design ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA KHOA ĐIỆN-ĐIỆN TỬ BỘ MÔN KỸ THUẬT ĐIỆN TỬ Embedded System Design Chapter 2: Microcontroller Series (Part 1) 1. Introduction to ARM processors 2.

More information

_äìéi~ä» stereo_headset application. Readme. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom

_äìéi~ä» stereo_headset application. Readme. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom _äìéi~ä» stereo_headset application Readme November 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 4187346 Tel: +44 (0)1223 692000 Fax: +44 (0)1223 692001

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP Digital Blocks Semiconductor IP TFT Controller General Description The Digital Blocks TFT Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 to a TFT panel. In an FPGA,

More information

Universität Dortmund. ARM Architecture

Universität Dortmund. ARM Architecture ARM Architecture The RISC Philosophy Original RISC design (e.g. MIPS) aims for high performance through o reduced number of instruction classes o large general-purpose register set o load-store architecture

More information

C O M P A N Y O V E R V I E W

C O M P A N Y O V E R V I E W C O M P A N Y O V E R V I E W Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core

More information

Digital IP Cell 8-bit Microcontroller PE80

Digital IP Cell 8-bit Microcontroller PE80 1. Description The is a Z80 compliant processor soft-macro - IP block that can be implemented in digital or mixed signal ASIC designs. The Z80 and its derivatives and clones make up one of the most commonly

More information

_äìé`çêé. Audio Compression Codec Specifications and Requirements. Application Note. Issue 2

_äìé`çêé. Audio Compression Codec Specifications and Requirements. Application Note. Issue 2 _äìé`çêé Audio Compression Codec Specifications and Requirements Application Note Issue 2 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 3665875 Tel: +44

More information

_äìéi~ä» Implementing Streams in BlueLab. User Guide. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom

_äìéi~ä» Implementing Streams in BlueLab. User Guide. November CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom _äìéi~ä» Implementing Streams in BlueLab User Guide November 2006 CSR Cambridge Science Park Milton Road Cambridge CB4 0WH United Kingdom Registered in England 4187346 Tel: +44 (0)1223 692000 Fax: +44

More information

Revolutionary Quad-Pipelined Ultra High Performance 16/32-bit Microcontroller v. 6.05

Revolutionary Quad-Pipelined Ultra High Performance 16/32-bit Microcontroller v. 6.05 DQ80251 Revolutionary Quad-Pipelined Ultra High Performance 16/32-bit Microcontroller v. 6.05 O V E R V I E W DQ80251 is a revolutionary Quad-Pipelined ultrahigh performance, speed optimized soft core,

More information

Design Tools for 100,000 Gate Programmable Logic Devices

Design Tools for 100,000 Gate Programmable Logic Devices esign Tools for 100,000 Gate Programmable Logic evices March 1996, ver. 1 Product Information Bulletin 22 Introduction The capacity of programmable logic devices (PLs) has risen dramatically to meet the

More information

OUTLINE. STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and Pipelining Cortex-M0 Programming Model Toolchain and Project Structure

OUTLINE. STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and Pipelining Cortex-M0 Programming Model Toolchain and Project Structure ARCHITECTURE AND PROGRAMMING George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners OUTLINE STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and

More information

COMPLEX EMBEDDED SYSTEMS

COMPLEX EMBEDDED SYSTEMS COMPLEX EMBEDDED SYSTEMS Embedded System Design and Architectures Summer Semester 2012 System and Software Engineering Prof. Dr.-Ing. Armin Zimmermann Contents System Design Phases Architecture of Embedded

More information

18-349: Embedded Real-Time Systems Lecture 2: ARM Architecture

18-349: Embedded Real-Time Systems Lecture 2: ARM Architecture 18-349: Embedded Real-Time Systems Lecture 2: ARM Architecture Anthony Rowe Electrical and Computer Engineering Carnegie Mellon University Basic Computer Architecture Embedded Real-Time Systems 2 Memory

More information

CROSSWARE 7 V8051NT Virtual Workshop for Windows. q Significantly reduces software development timescales

CROSSWARE 7 V8051NT Virtual Workshop for Windows. q Significantly reduces software development timescales CROSSWARE 7 V8051NT HIGHLIGHTS q Significantly reduces software development timescales q Enables debug and verification without hardware q Allows programmers to simulate complete target system 8051 Virtual

More information

atoll ic TrueSTUDIOPro Professional C/C++ IDE for ARM -based devices The essential toolkit for ARM development

atoll ic TrueSTUDIOPro Professional C/C++ IDE for ARM -based devices The essential toolkit for ARM development atoll ic TrueSTUDIOPro Professional C/C++ IDE for ARM -based devices The essential toolkit for ARM development Atollic TrueSTUDIO Pro The Atollic TrueSTUDIO Pro IDE is a powerful C/C++ development tool

More information

FPGA-Based Embedded Systems for Testing and Rapid Prototyping

FPGA-Based Embedded Systems for Testing and Rapid Prototyping FPGA-Based Embedded Systems for Testing and Rapid Prototyping Martin Panevsky Embedded System Applications Manager Embedded Control Systems Department The Aerospace Corporation Flight Software Workshop

More information

ADPCM-LCO Voice Compression Logic Core

ADPCM-LCO Voice Compression Logic Core ADPCM-LCO Voice Compression Logic Core Functional Description The ADPCM-LCO logic core [Adaptive Differential Pulse Code Modulation-Low Channel count Optimized] is a peripheral for digital voice compression/de-compression

More information

ELCT 912: Advanced Embedded Systems

ELCT 912: Advanced Embedded Systems ELCT 912: Advanced Embedded Systems Lecture 2-3: Embedded System Hardware Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering Embedded System Hardware Used for processing of

More information

Custom Design Formal Equivalence Checking Based on Symbolic Simulation. Overview. Verification Scope. Create Verilog model. Behavioral Verilog

Custom Design Formal Equivalence Checking Based on Symbolic Simulation. Overview. Verification Scope. Create Verilog model. Behavioral Verilog DATASHEET Custom Design Formal Equivalence Checking Based on Symbolic Simulation High-quality equivalence checking for full-custom designs Overview is an equivalence checker for full custom designs. It

More information

Overview of Microcontroller and Embedded Systems

Overview of Microcontroller and Embedded Systems UNIT-III Overview of Microcontroller and Embedded Systems Embedded Hardware and Various Building Blocks: The basic hardware components of an embedded system shown in a block diagram in below figure. These

More information

USB / Ethernet Production Ready Module

USB / Ethernet Production Ready Module USB / Ethernet Production Ready Module The USB / Ethernet module is a single board containing everything needed to add highperformance Internet and USB connectivity to customers system designs without

More information

In Circuit Emulators. In-Circuit Emulators.

In Circuit Emulators. In-Circuit Emulators. In Circuit Emulators An ideal tool is one that provides visibility into the internal operation of the device or component being emulated. In circuit emulators are hardware tools that both provide that

More information

Reviving Bit-slice Technology in a Programmable Fashion

Reviving Bit-slice Technology in a Programmable Fashion By Andrew Siska, Applications Engineer Sr Staff, and Meng He, Product Marketing Engineer Sr, Cypress Semiconductor Corp. The term Bit Slicing was once dominant in history books as a technique for constructing

More information

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes Presented at Design Automation Conference (DAC) San Francisco, CA, June 4, 2012. Presented by Chuck Cruse FPGA Hardware

More information

DQSPI IP Core. Serial Peripheral Interface Master/Slave with single, dual and quad SPI Bus support v. 2.01

DQSPI IP Core. Serial Peripheral Interface Master/Slave with single, dual and quad SPI Bus support v. 2.01 017 DQSPI IP Core Serial Peripheral Interface Master/Slave with single, dual and quad SPI Bus support v..01 C O M P A N Y O V E R V I E W Digital Core Design is a leading IP Core provider and a System-on-Chip

More information

Designing with Nios II Processor for Hardware Engineers

Designing with Nios II Processor for Hardware Engineers Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under

More information

Design Once with Design Compiler FPGA

Design Once with Design Compiler FPGA Design Once with Design Compiler FPGA The Best Solution for ASIC Prototyping Synopsys Inc. Agenda Prototyping Challenges Design Compiler FPGA Overview Flexibility in Design Using DC FPGA and Altera Devices

More information

Lecture 1. Course Overview and The 8051 Architecture

Lecture 1. Course Overview and The 8051 Architecture Lecture 1 Course Overview and The 8051 Architecture MCUniversity Program Lectures 8051 architecture t System overview of C8051F020 8051 instruction set System clock, crossbar and GPIO Assembler directives

More information

Security is our priority

Security is our priority Security is our priority OUR VALUES Serve others, not yourself Be safe, be healthy Do the right thing Be empowered and accountable Be curious beyond the obvious Enjoy what you do and celebrate who we are

More information

Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.

Intelop. *As new IP blocks become available, please contact the factory for the latest updated info. A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment

More information

Growth outside Cell Phone Applications

Growth outside Cell Phone Applications ARM Introduction Growth outside Cell Phone Applications ~1B units shipped into non-mobile applications Embedded segment now accounts for 13% of ARM shipments Automotive, microcontroller and smartcards

More information

ECE254 Lab3 Tutorial. Introduction to MCB1700 Hardware Programming. Irene Huang

ECE254 Lab3 Tutorial. Introduction to MCB1700 Hardware Programming. Irene Huang ECE254 Lab3 Tutorial Introduction to MCB1700 Hardware Programming Irene Huang Lab3 Requirements : API Dynamic Memory Management: void * os_mem_alloc (int size, unsigned char flag) Flag takes two values:

More information

RM3 - Cortex-M4 / Cortex-M4F implementation

RM3 - Cortex-M4 / Cortex-M4F implementation Formation Cortex-M4 / Cortex-M4F implementation: This course covers both Cortex-M4 and Cortex-M4F (with FPU) ARM core - Processeurs ARM: ARM Cores RM3 - Cortex-M4 / Cortex-M4F implementation This course

More information

CZ80CPU 8-Bit Microprocessor Megafunction

CZ80CPU 8-Bit Microprocessor Megafunction CZ0CPU -Bit Microprocessor Megafunction General Description Implements a fast, fully-functional, single-chip, - bit microprocessor with the same instruction set as the Z0. The core has a 16-bit address

More information

Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim

Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937

More information

Cadence SystemC Design and Verification. NMI FPGA Network Meeting Jan 21, 2015

Cadence SystemC Design and Verification. NMI FPGA Network Meeting Jan 21, 2015 Cadence SystemC Design and Verification NMI FPGA Network Meeting Jan 21, 2015 The High Level Synthesis Opportunity Raising Abstraction Improves Design & Verification Optimizes Power, Area and Timing for

More information

R bit Microcontroller Megafunction

R bit Microcontroller Megafunction R0515 bit Microcontroller Megafunction General Description The R0515 is a fast, singlechip, bit microcontroller that executes all ASM51 uctions. It has the same uction set as the 0C31, but executes operations

More information

Pipelined High Performance 8-bit Microcontroller ver 3.10

Pipelined High Performance 8-bit Microcontroller ver 3.10 DP8051 Pipelined High Performance 8-bit Microcontroller ver 3.10 OVERVIEW DP8051 is an ultra high performance, speed optimized soft core of a single-chip 8- bit embedded controller dedicated for operation

More information

ALTERA M9K EMBEDDED MEMORY BLOCKS

ALTERA M9K EMBEDDED MEMORY BLOCKS ALTERA M9K EMBEDDED MEMORY BLOCKS M9K Overview M9K memories are Altera s embedded high-density memory arrays Nearly all modern FPGAs include something similar of varying sizes 8192 bits per block (9216

More information

Reminder. Course project team forming deadline. Course project ideas. Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline

Reminder. Course project team forming deadline. Course project ideas. Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline Reminder Course project team forming deadline Friday 9/8 11:59pm You will be randomly assigned to a team after the deadline Course project ideas If you have difficulty in finding team mates, send your

More information

Chapter 4. Enhancing ARM7 architecture by embedding RTOS

Chapter 4. Enhancing ARM7 architecture by embedding RTOS Chapter 4 Enhancing ARM7 architecture by embedding RTOS 4.1 ARM7 architecture 4.2 ARM7TDMI processor core 4.3 Embedding RTOS on ARM7TDMI architecture 4.4 Block diagram of the Design 4.5 Hardware Design

More information

ADPCM-HCO Voice Compression Logic Core

ADPCM-HCO Voice Compression Logic Core ADPCM-HCO Voice Compression Logic Core Functional Description The ADPCM-HCO logic core [Adaptive Differential Pulse Code Modulation-High Channel count Optimized] is a peripheral for digital voice compression

More information

White Paper Bluetooth Protocol Stack technology from IAR Systems

White Paper Bluetooth Protocol Stack technology from IAR Systems 111111 White Paper Bluetooth Protocol Stack technology from IAR Systems Issue 1.0 2001-05-22 CONTENT INTRODUCTION 3 WHAT IS A BLUETOOTH PROTOCOL STACK? 3 HOW TO SELECT A BLUETOOTH PROTOCOL STACK? 5 Tool

More information

Pearson New International Edition. The 8051 Microcontroller and Embedded Systems Mazidi Mazidi McKinlay Second Edition

Pearson New International Edition. The 8051 Microcontroller and Embedded Systems Mazidi Mazidi McKinlay Second Edition Pearson New International Edition The 8051 Microcontroller and Embedded Systems Mazidi Mazidi McKinlay Second Edition Pearson Education Limited Edinburgh Gate Harlow Essex CM20 2JE England and Associated

More information

Bluetooth Smart: How to avoid making dumb devices

Bluetooth Smart: How to avoid making dumb devices Bluetooth Smart: How to avoid making dumb devices CONNECTED DEVICES Bluetooth Smart: How to avoid making dumb devices white paper Development activity for new Bluetooth Smart devices rocketed after Apple

More information

ARM ARCHITECTURE. Contents at a glance:

ARM ARCHITECTURE. Contents at a glance: UNIT-III ARM ARCHITECTURE Contents at a glance: RISC Design Philosophy ARM Design Philosophy Registers Current Program Status Register(CPSR) Instruction Pipeline Interrupts and Vector Table Architecture

More information

Moodle WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics

Moodle WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics Moodle 4 WILLINGDON COLLEGE SANGLI (B. SC.-II) Digital Electronics Advanced Microprocessors and Introduction to Microcontroller Moodle developed By Dr. S. R. Kumbhar Department of Electronics Willingdon

More information

ID 321L: KPIT GNU compiler plug-ins for HEW / KPIT Eclipse IDE

ID 321L: KPIT GNU compiler plug-ins for HEW / KPIT Eclipse IDE ID 321L: KPIT GNU compiler plug-ins for HEW / KPIT Eclipse IDE Matt Newsome, Principal Engineer, Software Tools, Renesas Electronics Europe, UK Kaushik Phatak, Tech Lead, KPIT Cummins Infosystems, Pune,

More information

ENE 334 Microprocessors

ENE 334 Microprocessors Page 1 ENE 334 Microprocessors Lecture 7: MCS-51 Architecture I : Dejwoot KHAWPARISUTH http://webstaff.kmutt.ac.th/~dejwoot.kha/ ENE 334 MCS-51 Architecture I Page 2 Outlines: 8051 Microcontroller Hardware

More information

Computer and Hardware Architecture I. Benny Thörnberg Associate Professor in Electronics

Computer and Hardware Architecture I. Benny Thörnberg Associate Professor in Electronics Computer and Hardware Architecture I Benny Thörnberg Associate Professor in Electronics Hardware architecture Computer architecture The functionality of a modern computer is so complex that no human can

More information

SpaceWire Router ASIC

SpaceWire Router ASIC SpaceWire Router ASIC Steve Parkes, Chris McClements Space Technology Centre, University of Dundee Gerald Kempf, Christian Toegel Austrian Aerospace Stephan Fisher Astrium GmbH Pierre Fabry, Agustin Leon

More information

Modular ARM System Design

Modular ARM System Design An ARM Approved Training Partner for more than 7 years, Doulos has delivered ARM training in more than half of the world's top ten semiconductor companies. Doulos is the only ARM Approved Training partner

More information

HB0801 MiV_RV32IMAF_L1_AHB V2.0 Handbook

HB0801 MiV_RV32IMAF_L1_AHB V2.0 Handbook HB0801 MiV_RV32IMAF_L1_AHB V2.0 Handbook 11 2017 Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for

More information

Contents of this presentation: Some words about the ARM company

Contents of this presentation: Some words about the ARM company The architecture of the ARM cores Contents of this presentation: Some words about the ARM company The ARM's Core Families and their benefits Explanation of the ARM architecture Architecture details, features

More information

A Design of Transputer Core and its implementation in an FPGA

A Design of Transputer Core and its implementation in an FPGA Communicating Process Architectures 2004 Ian East, Jeremy Martin, Peter Welch, David Duce, and Mark Green (Eds.) IOS Press, 2004 1 A Design of Transputer Core and its implementation in an FPGA Makoto Tanaka,

More information

Arm Architecture. Enrique Secanechia Santos, Kevin Mesolella

Arm Architecture. Enrique Secanechia Santos, Kevin Mesolella Arm Architecture Enrique Secanechia Santos, Kevin Mesolella Outline History What is ARM? What uses ARM? Instruction Set Registers ARM specific instructions/implementations Stack Interrupts Pipeline ARM

More information

Reminder. Course project team forming deadline. Course project ideas. Next milestone

Reminder. Course project team forming deadline. Course project ideas. Next milestone Reminder Course project team forming deadline Thursday 9/6 11:59pm You will be randomly assigned to a team after the deadline Course project ideas If you have difficulty in finding team mates, send your

More information

ZAP Cross Debuggers for Motorola Microcontrollers

ZAP Cross Debuggers for Motorola Microcontrollers ZAP Cross Debuggers for Motorola Microcontrollers ZAP is a family of full-featured C and assembly language source-level debuggers designed to give Motorola embedded microcontroller developers a consistent

More information

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5.

2. List the five interrupt pins available in INTR, TRAP, RST 7.5, RST 6.5, RST 5.5. DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EE6502- MICROPROCESSORS AND MICROCONTROLLERS UNIT I: 8085 PROCESSOR PART A 1. What is the need for ALE signal in

More information

Ciphertext. data out. Plaintext. data out

Ciphertext. data out. Plaintext. data out Technology PRODUCT BRIEF IP cores for ASIC Features Implements (Rijndael) to NIST FIPS PUB 197 Plaintext data in Key in Ciphertext data in Key Expansion Decryption Ciphertext data out Plaintext data out

More information

Chapter 2 Getting Hands on Altera Quartus II Software

Chapter 2 Getting Hands on Altera Quartus II Software Chapter 2 Getting Hands on Altera Quartus II Software Contents 2.1 Installation of Software... 20 2.2 Setting Up of License... 21 2.3 Creation of First Embedded System Project... 22 2.4 Project Building

More information

AL8253 Core Application Note

AL8253 Core Application Note AL8253 Core Application Note 6-15-2012 Table of Contents General Information... 3 Features... 3 Block Diagram... 3 Contents... 4 Behavioral... 4 Synthesizable... 4 Test Vectors... 4 Interface... 5 Implementation

More information

L2 - C language for Embedded MCUs

L2 - C language for Embedded MCUs Formation C language for Embedded MCUs: Learning how to program a Microcontroller (especially the Cortex-M based ones) - Programmation: Langages L2 - C language for Embedded MCUs Learning how to program

More information

I 2 C Bus Interface - Slave ver 3.08

I 2 C Bus Interface - Slave ver 3.08 DI2CS I 2 C Bus Interface - Slave ver 3.08 OVERVIEW I 2 C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices.

More information

Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02

Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02 Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC

More information

Microprocessors and Microcontrollers. Assignment 1:

Microprocessors and Microcontrollers. Assignment 1: Microprocessors and Microcontrollers Assignment 1: 1. List out the mass storage devices and their characteristics. 2. List the current workstations available in the market for graphics and business applications.

More information

CISC RISC. Compiler. Compiler. Processor. Processor

CISC RISC. Compiler. Compiler. Processor. Processor Q1. Explain briefly the RISC design philosophy. Answer: RISC is a design philosophy aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed. The RISC

More information

Integrated Circuit ORB (ICO) White Paper V1.1

Integrated Circuit ORB (ICO) White Paper V1.1 Integrated Circuit (ICO) White Paper V1.1 F. Humcke and D. Paniscotti PrismTech Corporation SYNOPSIS This white paper presents a detailed overview of PrismTech s Integrated Circuit (ICO) and describes

More information

Latches. IT 3123 Hardware and Software Concepts. Registers. The Little Man has Registers. Data Registers. Program Counter

Latches. IT 3123 Hardware and Software Concepts. Registers. The Little Man has Registers. Data Registers. Program Counter IT 3123 Hardware and Software Concepts Notice: This session is being recorded. CPU and Memory June 11 Copyright 2005 by Bob Brown Latches Can store one bit of data Can be ganged together to store more

More information

FPGA design with National Instuments

FPGA design with National Instuments FPGA design with National Instuments Rémi DA SILVA Systems Engineer - Embedded and Data Acquisition Systems - MED Region ni.com The NI Approach to Flexible Hardware Processor Real-time OS Application software

More information

DS-XA In-Circuit Emulator

DS-XA In-Circuit Emulator DS-XA In-Circuit Emulator In-Circuit Emulator for Philips XA Microcontrollers FEATURES Emulates XA Derivatives 2MByte Code and Data Memory Memory With Mapping Capabilities Real-Time Trace Frequency Range

More information

Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition

Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition FPGA Design Philip Andrew Simpson FPGA Design Best Practices for Team-based Reuse Second Edition Philip Andrew Simpson San Jose, CA, USA ISBN 978-3-319-17923-0 DOI 10.1007/978-3-319-17924-7 ISBN 978-3-319-17924-7

More information

Keysight U5340A FPGA Development Kit for High-Speed Digitizers

Keysight U5340A FPGA Development Kit for High-Speed Digitizers Keysight U5340A FPGA Development Kit for High-Speed Digitizers 02 Keysight U5340A FPGA Development Kit for High-Speed Digitizers - Brochure Helping You Achieve Greater Performance The FPGA Development

More information

ARM996HS. The First Licensable, Clockless 32-bit Processor Core

ARM996HS. The First Licensable, Clockless 32-bit Processor Core ARM996HS The First Licensable, Clockless 32-bit Processor Core Arjan Bink, ARM996HS Technical Lead, Handshake Solutions Richard York, CPU Product Manager, ARM ARM - Handshake Solutions Partnership Announced

More information

ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7

ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7 ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7 Scherer Balázs Budapest University of Technology and Economics Department of Measurement and Information Systems BME-MIT 2018 Trends of 32-bit microcontrollers

More information

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss Grundlagen Microcontroller Interrupts Günther Gridling Bettina Weiss 1 Interrupts Lecture Overview Definition Sources ISR Priorities & Nesting 2 Definition Interrupt: reaction to (asynchronous) external

More information

ALTERA FPGA Design Using Verilog

ALTERA FPGA Design Using Verilog ALTERA FPGA Design Using Verilog Course Description This course provides all necessary theoretical and practical know-how to design ALTERA FPGA/CPLD using Verilog standard language. The course intention

More information

The Central Processing Unit

The Central Processing Unit The Central Processing Unit All computers derive from the same basic design, usually referred to as the von Neumann architecture. This concept involves solving a problem by defining a sequence of commands

More information

PINE TRAINING ACADEMY

PINE TRAINING ACADEMY PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation

More information

Digital Blocks Semiconductor IP

Digital Blocks Semiconductor IP 805 SFR Bus Digital Blocks Semiconductor IP 805 Microcontroller Configurable Peripherals General Description The Digital Blocks (Configurable Peripherals) Microcontroller Verilog IP Core is complaint with

More information

Configurable UART with FIFO ver 2.20

Configurable UART with FIFO ver 2.20 D16550 Configurable UART with FIFO ver 2.20 OVERVIEW The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial

More information

ZAP Cross Debuggers for STMicroelectronics Microcontrollers

ZAP Cross Debuggers for STMicroelectronics Microcontrollers ZAP Cross Debuggers for STMicroelectronics Microcontrollers ZAP is a family of full-featured C and assembly language source-level debuggers designed to give STMicroelectronics embedded microcontroller

More information