Beyond Pipelining. CP-226: Computer Architecture. Lecture 23 (19 April 2013) CADSL

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1 Beyond Pipelining Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay CP-226: Computer Architecture Lecture 23 (19 April 2013)

2 0-25 Jump Shift 4 Add RegDst opcode left 2 CONTROL Branch ALU 1 mux 0 0 mux 1 MemtoReg PC Instr. mem. Combined Datapaths Sign ext. 1 mux 0 Reg. File Shift left 2 1 mux 0 ALU ALU Cont. zero MemWrite MemRead Data mem. 0 mux Feb 2013 Computer Architecture@MNIT 2

3 Single-Cycle Datapath Instruction class Instr. fetch (IF) Instr. Decode (also reg. file read) (ID) Execution (ALU Operation) (EX) Data access (MEM) Write Back (Reg. file write) (WB) Total time lw 1ns 1ns 8ns sw 1ns 8ns R-format add, sub, and, or, slt 1ns 1ns 8ns B-format, beq 1ns 8ns No operation on data; idle time equalizes instruction length to a fixed clock period. 19 Feb 2013 Computer Architecture@MNIT 3

4 Multicycle Datapath PCSource IorD out MUX in1 PCWrite etc. PC in2 control Data Addr. Memory to Control FSM Instr. reg. (IR) IRWrite Mem. Data (MDR) Register file RegDst RegWrite B Reg. A Reg. ALUSrcA ALUSrcB Shift left ALU ALUOut Reg. MemRead MemWrite MemtoReg Sign extend Shift left 2 ALU control ALUOp 19 Feb 2013 Computer Architecture@MNIT 4

5 Traffic Flow 19 Apr 2013 Computer 5

6 Pipelined Datapath Instruction class Instr. fetch (IF) Instr. Decode (also reg. file read) (ID) Execution (ALU Operation) (EX) Data access (MEM) Write Back (Reg. file write) (WB) Total time lw 1ns 1ns 10ns sw 1ns 1ns 10ns R-format: add, sub, and, or, slt 1ns 1ns 10ns B-format: beq 1ns 1ns 10ns No operation on data; idle time inserted to equalize instruction lengths. 19 Apr 2013 Computer 6

7 Pipelined Datapath PC 4 Add Instr mem for R-type for I-type lw IF/ID ID/EX EX/MEM MEM/WB opcode Reg. File Sign ext. Shift left 2 1 mux 0 ALU ALU zero 1 mux 0 Data mem. 0 mux Apr 2013 Computer Architecture@MNIT 7

8 Single Lane Traffic 19 Apr 2013 Computer 8

9 Memory Performance Gap 19 Apr 2013 Computer 9

10 Memory Hierarchy Temporal Locality Keep recently referenced items at higher levels Future references sahsfied quickly CPU I & D L1 Cache Shared L2 Cache SpaHal Locality Bring neighbors of recently referenced to higher levels Future references sahsfied quickly Main Memory Disk 19 Apr 2013 Computer Architecture@MNIT 10

11 Limits of Pipelining IBM RISC Experience Control and data dependences add 15% Best case CPI of 1.15, IPC of 0.87 Deeper pipelines (higher frequency) magnify dependence penalhes This analysis assumes 100% cache hit rates Hit rates approach 100% for some programs Many important programs have much worse hit rates 19 Apr 2013 Computer 11

12 Processor Performance Time Processor Performance = Program Instructions Cycles =! X! X! Program Instruction (code size) (CPI) In the 1980 s (decade of pipelining): CPI: 5.0 => 1.15 In the 1990 s (decade of superscalar): CPI: 1.15 => 0.5 (best case) In the 2000 s (decade of mulhcore): Marginal CPI improvement 19 Apr 2013 Computer Architecture@MNIT 12 Time Cycle (cycle time)

13 Limits on InstrucHon Level Parallelism (ILP) Weiss and Smith [1984] 1.58 Sohi and Vajapeyam [1987] 1.81 Tjaden and Flynn [1970] 1.86 (Flynn s bottleneck) Tjaden and Flynn [1973] 1.96 Uht [1986] 2.00 Smith et al. [1989] 2.00 Jouppi and Wall [1988] 2.40 Johnson [1991] 2.50 Acosta et al. [1986] 2.79 Wedig [1982] 3.00 Butler et al. [1991] 5.8 Melvin and Patt [1991] 6 Wall [1991] 7 (Jouppi disagreed) Kuck et al. [1972] 8 Riseman and Foster [1972] 51 (no control dependences) Nicolau and Fisher [1984] 90 (Fisher s optimism) 19 Apr 2013 Computer Architecture@MNIT 13

14 Superscalar Proposal Go beyond single instruchon pipeline, achieve IPC > 1 Dispatch mulhple instruchons per cycle Provide more generally applicable form of concurrency (not just vectors) Geared for sequenhal code that is hard to parallelize otherwise Exploit fine- grained or instruchon- level parallelism (ILP) 19 Apr 2013 Computer Architecture@MNIT 14

15 Classifying ILP Machines [Jouppi, DECWRL 1991] Baseline scalar RISC Issue parallelism = IP = 1 OperaHon latency = OP = 1 Peak IPC = 1 SUCCESSIVE INSTRUCTIONS IF DE EX WB TIME IN CYCLES (OF BASELINE MACHINE) 19 Apr 2013 Computer Architecture@MNIT 15

16 Classifying ILP Machines [Jouppi, DECWRL 1991] Superpipelined: cycle Hme = 1/m of baseline Issue parallelism = IP = 1 inst / minor cycle OperaHon latency = OP = m minor cycles Peak IPC = m instr / major cycle (m x speedup?) IF DE EX WB Apr 2013 Computer Architecture@MNIT 16

17 Classifying ILP Machines [Jouppi, DECWRL 1991] Superscalar: Issue parallelism = IP = n inst / cycle OperaHon latency = OP = 1 cycle Peak IPC = n instr / cycle (n x speedup?) IF DE EX WB 19 Apr 2013 Computer Architecture@MNIT 17

18 Classifying ILP Machines [Jouppi, DECWRL 1991] VLIW: Very Long InstrucHon Word Issue parallelism = IP = n inst / cycle OperaHon latency = OP = 1 cycle Peak IPC = n instr / cycle = 1 VLIW / cycle IF DE WB EX 19 Apr 2013 Computer Architecture@MNIT 18

19 Classifying ILP Machines [Jouppi, DECWRL 1991] Superpipelined- Superscalar Issue parallelism = IP = n inst / minor cycle OperaHon latency = OP = m minor cycles Peak IPC = n x m instr / major cycle IF DE EX WB 19 Apr 2013 Computer Architecture@MNIT 19

20 Superscalar vs. Superpipelined Roughly equivalent performance If n = m then both have about the same IPC Parallelism exposed in space vs. Hme SUPERSCALAR Key: SUPERPIPELINED IFetch Dcode Execute Writeback Time in Cycles (of Base Machine) Apr 2013 Computer Architecture@MNIT 20

21 LimitaHons of Scalar Pipelines Scalar upper bound on throughput IPC <= 1 or CPI >= 1 Inefficient unified pipeline Long latency for each instruchon Rigid pipeline stall policy One stalled instruchon stalls all newer instruchons 19 Apr 2013 Computer Architecture@MNIT 21

22 Instruction-Level Parallelism When exploihng instruchon- level parallelism, goal is to maximize IPC Pipeline IPC = Ideal pipeline IPC + Structural stalls - Data hazard stalls - Control stalls - Parallelism with basic block is limited Typical size of basic block = 3-6 instruchons Must ophmize across branches 19 Apr 2013 Computer Architecture@MNIT 22

23 LimitaHons of Scalar Pipelines Scalar upper bound on throughput IPC <= 1 or CPI >= 1 Inefficient unified pipeline Long latency for each instruchon Rigid pipeline stall policy One stalled instruchon stalls all newer instruchons 19 Apr 2013 Computer Architecture@MNIT 23

24 Superscalar Architecture Ø Simple concept Ø Wide pipeline Ø InstrucHons are not independent Ø Superscalar architecture is natural descendant of pipelined scalar RISC Ø Superscalar techniques largely concern the processor organizahon, independent of the ISA and the other architectural features Ø Thus, possibility to develop a processor code compahble with an exishng architecture 19 Apr 2013 Computer Architecture@MNIT 24

25 Superscalar Pipelines IF ID RD ALU MEM WB 19 Apr 2013 Computer 25

26 Highway 19 Apr 2013 Computer 26

27 Instruction Level Parallelism Ø InstrucHon parallelism of a program is a measure of the average number of instruchons that a superscalar processor might be able to execute at the same Hme Ø Mostly, ILP is determined by the number of true dependencies and the number of branches in relahon to other instruchons 19 Apr 2013 Computer Architecture@MNIT 27

28 Machine Level Parallelism Ø Machine parallelism of a processor is a measure of the ability of processor to take advantage of the ILP Ø Determined by the number of instruchons that can be fetched and executed at the same Hme Ø A challenge in the design of superscalar processor is to achieve good balance between instruchon parallelism and machine parallelism 19 Apr 2013 Computer Architecture@MNIT 28

29 Superscalar Pipelines IF ID RD ALU MEM WB 19 Apr 2013 Computer 29

30 Highway 19 Apr 2013 Computer 30

31 Dream Highway 19 Apr 2013 Computer 31

32 Superscalar Pipelines Dynamic Pipelines 1. Alleviate the limitahons of pipelined implementahon 2. Use diversified pipelines 3. Temporal machine parallelism 19 Apr 2013 Computer 32

33 Superscalar Pipelines (Diversified) IF ID RD EX ALU Mem1 FP1 FP2 BR Mem2 FP3 WB 19 Apr 2013 Computer 33

34 Superscalar Pipelines (Diversified) Diversified Pipelines v Each pipeline can be customized for parhcular instruchon type v Each instruchon type incurs only necessary latency v Certainly less expensive than idenhcal copies v If all inter- instruchon dependencies are resolved then there is no stall aqer instruchon issue Require special considerahon Ø Number and Mix of funchonal units 19 Apr 2013 Computer Architecture@MNIT 34

35 Superscalar Architecture InstrucHon issue and machine parallelism Ø ILP is not necessarily exploited by widening the pipelines and adding more resources Ø Processor policies towards fetching decoding, and execuhng instruchon have significant effect on its ability to discover instruchons which can be executed concurrently Ø InstrucHon issue is refer to the process of inihahng instruchon execuhon Ø InstrucHon issue policy limits or enhances performance because it determines the processor s look ahead capability 19 Apr 2013 Computer Architecture@MNIT 35

36 Super-scalar Architecture Fetch Instruction buffer Decode Dispatch buffer Dispatch Issue Reservation station Execute finish Complete Re-order/Completion buffer Store buffer Retire 19 Apr 2013 Computer 36

37 Superscalar Pipeline Stages Fetch Instruction Buffer In Program Order Out of Order In Program Order Decode Dispatch Execute Complete Retire Dispatch Buffer Issuing Buffer Completion Buffer Store Buffer 19 Apr 2013 Computer 37

38 Thank You 19 Apr 2013 Computer 38

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