Simulator for TriCore

Transcription

1 Simulator for TriCore TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for TriCore... 1 TRACE32 Simulator License... 4 Brief Overview of Documents for New Users... 5 Example Scripts... 5 Quick Start Select the Device Prompt B: for the ICD Debugger 6 2. Select the CPU Type to load the CPU specific Settings 6 3. Enter Debug Mode 6 4. Load your Application Program 6 5. Write a Start-up Script 7 OCDS-L1 Debugger... 8 Troubleshooting 8 Memory Classes 9 Breakpoints 10 Examples for Breakpoints 10 Trace FAQ CPU specific Trace Commands Analyzer.Mode PCP Select PCP trace 13 SYStem.Option DataTrace Enable data tracing 13 SYStem.Option INTSTART Start address of interrupt routines 13 SYStem.Option INTUSE Number of implemented interrupts 13 SYStem.Option MCDSKeyHigh Key (high part) for unlocking MCDS 13 SYStem.OptionMCDSKeyLow Key (low part) for unlocking MCDS 13 SYStem.Option TRAPSTART Start address of trap vectors 13 CPU specific SYStem Commands SYStem.BdmClock Define JTAG frequency 14 SYStem.CONFIG Configure debugger according to target topology 14 SYStem.CONFIG.DAP.BreakPINS Define mapping of break pins 14 SYStem.CONFIG.DAP.DAPENable Enable DAP mode on PORST 14 Simulator for TriCore 1

2 SYStem.CONFIG.DAP.USERn Configure and set USER pins 14 SYStem.CONFIG.Interface Set debug cable interface mode 14 SYStem.CPU Select CPU 15 SYStem.CpuAccess Run-time CPU access (intrusive) 15 SYStem.JtagClock Set the JTAG frequency 16 SYStem.LOCK Tristate the JTAG port 16 SYStem.MemAccess Run-time memory access (non-intrusive) 17 SYStem.Mode Establish the communication with the CPU 18 SYStem.Option CPU specific commands 19 SYStem.Option DCFREEZE Do not invalidate cache 19 SYStem.Option DIAG Diagnosis function 19 SYStem.Option DUALPORT Run-time memory access for all windows 19 SYStem.Option ETK Debugging together with ETK from ETAS 19 SYStem.Option HeartBeat Bug fix to avoid FPI bus conflict 20 SYStem.Option ICFLUSH Flush instruction cache at Go or Step 20 SYStem.Option IMASKASM Disable interrupts while single stepping 20 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 20 SYStem.Option PERSTOP Enable global peripheral suspend 20 SYStem.Option SOFTLONG Set 32 bit software breakpoints 20 SYStem.Option STEPSOFT Step with software breakpoints 20 SYStem.Option TB1766FIX Bug fix for some TC1766 TriBoards 20 SYStem.Option TC1796FIX Bug fix for disabling the watchdog 21 SYStem.Option TC19XXFIX Bug fix required for some TC19XX derivatives 21 SYStem.RESetOut Assert nreset/nsrst on JTAG connector 21 SYStem.Option WATCHDOGFIX Disables the watchdog on SYStem.Up 21 SYStem.state Open SYStem.state window 21 CPU specific TrOnchip Commands TrOnchip.BreakBusN.BreakIN Configure break pin of BreakBus N 22 TrOnchip.BreakBusN.BreakOUT Configure break pin of BreakBus N 22 TrOnchip.BreakIN.<target> Connect break target to BreakBus 22 TrOnchip.BreakOUT.<source> Connect break source to BreakBus 22 TrOnchip.CONVert Not relevant for the TRICORE architecture 22 TrOnchip.CountX Event X counter value 22 TrOnchip.CountY Event Y counter value 22 TrOnchip.EXTernal Configure TriCore break on BreakBus event 23 TrOnchip.RESet Reset settings for the on-chip trigger unit 23 TrOnchip.SusSWitch Enable or disable suspend switch 23 TrOnchip.SusSWitch.FORCE Force generation of suspend signal 23 TrOnchip.SusSWitch.Mode Set suspend switch mode 23 TrOnchip.SusTarget Connect special targets to the suspend bus 23 TrOnchip.TCompress Trace data compression 23 TrOnchip.TDelay Trace trigger delay (obsolete) 23 TrOnchip.TExtMode Mode for external trigger input 24 Simulator for TriCore 2

3 TrOnchip.TExtPol Polarity of external trigger input 24 TrOnchip.TMode Trace mode (obsolete) 24 TrOnchip.TR0 Specify trigger event 0 24 TrOnchip.TR1 Specify trigger event 1 24 TrOnchip.state Show on-chip trigger window 24 TrOnchip.X Select trigger source X 24 TrOnchip.Y Select trigger source Y 24 Support Available Tools 25 Compilers 28 Target Operating Systems 28 3rd Party Tool Integrations 29 Products Product Information 30 Order Information 30 Simulator for TriCore 3

4 Simulator for TriCore Version 06-Nov-2017 All general commands are described in the IDE Reference Guide (ide_ref.pdf) and General Commands Reference. This documentation describes the processor specific settings and features for the SIM TRICORE. TRACE32 Simulator License [build DVD 02/2016] The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License. Simulator for TriCore 4

5 For more information, see Brief Overview of Documents for New Users Architecture-independent information: Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger. T32Start is only available for Windows. General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands. Architecture-specific information: Processor Architecture Manuals : These manuals describe commands that are specific for the processor architecture supported by your debug cable. To access the manual for your processor architecture, proceed as follows: - Choose Help menu > Processor Architecture Manual. RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware debugging. Example Scripts In your TRACE32 installation directory there is a subdirectory ~~/demo/tricore/ where you will find example scripts and demo software: compiler/ hardware/ simulator/ Compiler examples. The demo scripts usually also run in the simulator. Special simulator configuration. Simulator for TriCore 5

6 Quick Start This chapter should help you to prepare your Simulator for TriCore. For some applications additional steps might be necessary that are not described in this Quick Start section. See the Example Scripts for more examples. 1. Select the Device Prompt B: for the ICD Debugger B:: On all TRACE32 tool configurations except for the emulator device B:: is already selected. 2. Select the CPU Type to load the CPU specific Settings SYStem.CPU TC Enter Debug Mode SYStem.Up This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers. 4. Load your Application Program Data.LOAD.Elf myprog.elf ; ELF specifies the format, myprog is the file name The options of the Data.LOAD command depend on the file format generated by the compiler. For information on the compiler options refer to the section Compiler. A detailed description of the Data.LOAD command is given in General Commands Reference. Simulator for TriCore 6

7 5. Write a Start-up Script Now the quick start is done. If you were successful you can start to debug, it is recommended to prepare a PRACTICE script (*.cmm, ASCII file format) to be able to do all the necessary actions with only one command. Here is a typical start sequence: B:: WinCLEAR SYStem.CPU TC1766 SYStem.Up Data.LOAD.Elf myprog.elf ; Select the ICD device prompt ; Clear all windows ; Select CPU ; Reset the target and enter debug ; mode ; Load the application Data.List ; Open disassembly window *) Register /SpotLight ; Open register window *) Frame.view /Locals /Caller ; Open the stack frame with ; local variables *) Var.Watch %Spotlight flags ast ; Open watch window for variables *) PER.view Break.Set main Break.Set 0xD ; open window with peripheral register ; *) ; Set breakpoint to function main ; Set breakpoint to address ; 0xD *) These commands open windows on the screen. The window position can be specified with the WinPOS command. For information about how to build a PRACTICE script file (*.cmm file), refer to Debugger Basics - Training (training_debugger.pdf). There you can also find some information on basic actions with the debugger. Please keep in mind that only the Processor Architecture Manual (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice. Simulator for TriCore 7

8 OCDS-L1 Debugger Troubleshooting No information available. Simulator for TriCore 8

9 Memory Classes The following memory classes are available: Memory Class P D EEC Description Program Data Emulation Memory on EEC Only available on TriCore Emulation Devices for accessing the Emulation Extension Chip P: and D: display the same memory, the difference is in handling the symbols. Prepending an E as attribute to the memory class will make memory accesses possible even when the CPU is running. See SYStem.MemAccess and SYStem.CpuAccess for more information. In the Simulator, all memories are dual-port capable by default. Simulator for TriCore 9

10 Breakpoints There are two types of breakpoints available: Software breakpoints and On-chip breakpoints. The simulator does not differ between software- and on-chip breakpoints. Examples for Breakpoints Examples for instruction breakpoints: Break.Set 0xD4001FD0 /Program ; breakpoint on instruction Examples for breakpoints on data: Break.Set 0xAFE10200 /Write ; data write access breakpoint Breakpoint on write access to 0xAFE Break.Set 0xAFE10400 /Read ; data read access breakpoint Breakpoint on read access to 0xAFE Simulator for TriCore 10

11 Trace The Simulator offers a complete Instruction and Data trace. Use Trace.List to display. Simulator for TriCore 11

12 FAQ No information available Simulator for TriCore 12

13 CPU specific Trace Commands Analyzer.Mode PCP Select PCP trace SYStem.Option DataTrace Enable data tracing SYStem.Option INTSTART Start address of interrupt routines SYStem.Option INTUSE Number of implemented interrupts SYStem.Option MCDSKeyHigh Key (high part) for unlocking MCDS SYStem.OptionMCDSKeyLow Key (low part) for unlocking MCDS SYStem.Option TRAPSTART Start address of trap vectors Simulator for TriCore 13

14 CPU specific SYStem Commands SYStem.BdmClock Define JTAG frequency Obsolete command syntax. It has the same effect as SYStem.JtagClock. SYStem.CONFIG Configure debugger according to target topology The SYStem.CONFIG commands have no effect in Simulator. These commands describe the physical configuration at the JTAG port and the trace port of a multi-core hardware target. Since the simulator normally just simulates the instruction set, these commands will be ignored. Refer to the relevant Processor Architecture Manual in case you want to know the effect of these commands on a debugger. SYStem.CONFIG.DAP.BreakPINS Define mapping of break pins SYStem.CONFIG.DAP.DAPENable Enable DAP mode on PORST SYStem.CONFIG.DAP.USERn Configure and set USER pins SYStem.CONFIG.Interface Set debug cable interface mode Simulator for TriCore 14

15 SYStem.CPU Select CPU Format: SYStem.CPU <cpu> <cpu>: RIDERD TC10GP TC11IB TC1100 TC1115 TC1130 TC1161 TC1162 TC1163 TC1164 TC1165 TC1166 TC1762 TC1764 TC1765 TC1766 TC1766ED TC1775 TC1775B TC1736 TC1767 TC1767ED TC1792 TC1796 TC1796ED TC1797 TC1797ED TC1910 TC1912 TC1920A TC1920B PXB4260 CARMEL CERBERUS CERBERUS2 Default: TC1796. Selects the processor type. SYStem.CpuAccess Run-time CPU access (intrusive) Format: SYStem.CpuAccess <mode> <mode>: Enable Denied Nonstop Default: Denied. This option declares if an intrusive memory access can take place while the CPU is executing code. To perform this access, the debugger stops the CPU shortly, performs the access and then restarts the CPU. The run-time memory access has to be activated for each window by using the memory class E: (e.g. Data.dump ED:0xA ) or by using the format option %E (e.g. Var.View %E var1). Enable Stop the CPU shortly to perform a memory read or write while the program execution is running. Each short stop takes ms depending on the speed of the debug interface and on the size of the read/write accesses required. Simulator for TriCore 15

16 Denied Nonstop No intrusive memory read or write is possible while the CPU is executing the program. The program execution can not be stopped and the real-time behavior of the CPU is not affected. Nonstop reduces the functionality of the debugger to: run-time access to memory and variables trace display The debugger inhibits the following: to stop the program execution all features of the debugger that are intrusive (e.g. spot breakpoints, performance analysis via StopAndGo, conditional breakpoints etc.) SYStem.JtagClock Set the JTAG frequency SYStem.LOCK Tristate the JTAG port Simulator for TriCore 16

17 SYStem.MemAccess Run-time memory access (non-intrusive) Format: SYStem.MemAccess <mode> SYStem.ACCESS (deprecated) <mode>: CPU Denied Default: CPU. This option declares if and how a non-intrusive memory access can take place while the CPU is executing code. Although the CPU is not halted, run-time memory access creates an additional load on the processor s internal data bus. The MemAccess mode is printed in the state line. The run-time memory access has to be activated for each window by using the memory class E: (e.g. Data.dump ED:0xA ) or by using the format option %E (e.g. Var.View %E var1). It is also possible to enable non-intrusive memory access for all memory areas displayed by setting SYStem.Option DUALPORT ON. CPU Denied The debugger performs non-intrusive memory accesses via the CPU internal buses (FPI Bus). Non-intrusive memory access is disabled while the CPU is executing code. Instead intrusive accesses can be configured with SYStem.CpuAccess. SYStem.ACCESS is an alias for this command. Simulator for TriCore 17

18 SYStem.Mode Establish the communication with the CPU Format: SYStem.Mode <mode> <mode>: Down NoDebug Go Attach Up Down NoDebug Attach Go Up The CPU is held in reset, debug mode is not active. Default state and state after fatal errors. The CPU is running. Debug mode is not active, debug port is tristate. In this mode the target behaves as if the debugger is not connected. User program remains running (no reset) and the debug mode is activated. After this command the user program can be stopped with the break command or if any break condition occurs. The debugger should be in NoDebug mode when performing an Attach. The CPU is running. Debug mode is active. After this command the CPU can be stopped with the break command or if any break condition occurs. The CPU is not in reset but halted. Debug mode is active. In this mode the CPU can be started and stopped. This is the most typical way to activate debugging. Initial Mode: Down. The SYStem Modes are not only commands to bring the debugger in a certain debug state, they also reflect the current debug state of the target. SYStem Modes Attach and Go are only transitional states which will result in an Up state on success. Any critical failure will transition the debug state to SYStem Mode Down immediately The Emulate LED on the debug module is ON when the debug mode is active and the CPU is running. Simulator for TriCore 18

19 SYStem.Option CPU specific commands The SYStem.Option command group provides architecture and CPU specific commands. SYStem.Option DCFREEZE Do not invalidate cache SYStem.Option DIAG Diagnosis function Format: SYStem.Option DIAG [<value>] [<param>] [<param>] [<param>] System Diagnosis functions. Please execute only when demanded by LAUTERBACH support engineer. Functionality is undocumented, can change without any notice and may bring the debugger software into an unstable state. Do not use in script files. SYStem.Option DUALPORT Run-time memory access for all windows Format: SYStem.Option DUALPORT [ON OFF] Default: OFF. Enable permanent non-intrusive memory access for all windows and memory accesses. Memory class E: does not have to be specified any more. This only works when SYStem.MemAccess is set to CPU. When this option is enabled, no Data.dump or Data.List windows must be opened while programming the on-chip flash. Otherwise flash operation will fail. SYStem.Option ETK Debugging together with ETK from ETAS Simulator for TriCore 19

20 SYStem.Option HeartBeat Bug fix to avoid FPI bus conflict SYStem.Option ICFLUSH Flush instruction cache at Go or Step SYStem.Option IMASKASM Disable interrupts while single stepping SYStem.Option IMASKHLL Disable interrupts while HLL single stepping SYStem.Option PERSTOP Enable global peripheral suspend SYStem.Option SOFTLONG Set 32 bit software breakpoints SYStem.Option STEPSOFT Step with software breakpoints SYStem.Option TB1766FIX Bug fix for some TC1766 TriBoards Simulator for TriCore 20

21 SYStem.Option TC1796FIX Bug fix for disabling the watchdog SYStem.Option TC19XXFIX derivatives Bug fix required for some TC19XX SYStem.RESetOut Assert nreset/nsrst on JTAG connector The command is ignored by the simulator. It is an allowed command that you can run scripts which have actually been made for a debugger. See the Processor Architecture Manual for more information about the effect there. SYStem.Option WATCHDOGFIX Disables the watchdog on SYStem.Up SYStem.state Open SYStem.state window Format: SYStem.state Opens the SYStem.state window with settings of CPU specific system commands. Settings can also be changed here. Simulator for TriCore 21

22 CPU specific TrOnchip Commands TrOnchip.BreakBusN.BreakIN Configure break pin of BreakBus N TrOnchip.BreakBusN.BreakOUT Configure break pin of BreakBus N TrOnchip.BreakIN.<target> Connect break target to BreakBus TrOnchip.BreakOUT.<source> Connect break source to BreakBus TrOnchip.CONVert Not relevant for the TRICORE architecture TrOnchip.CountX Event X counter value TrOnchip.CountY Event Y counter value Simulator for TriCore 22

23 TrOnchip.EXTernal Configure TriCore break on BreakBus event TrOnchip.RESet Reset settings for the on-chip trigger unit TrOnchip.SusSWitch Enable or disable suspend switch TrOnchip.SusSWitch.FORCE Force generation of suspend signal TrOnchip.SusSWitch.Mode Set suspend switch mode TrOnchip.SusTarget Connect special targets to the suspend bus TrOnchip.TCompress Trace data compression TrOnchip.TDelay Trace trigger delay (obsolete) Simulator for TriCore 23

24 TrOnchip.TExtMode Mode for external trigger input TrOnchip.TExtPol Polarity of external trigger input TrOnchip.TMode Trace mode (obsolete) TrOnchip.TR0 Specify trigger event 0 TrOnchip.TR1 Specify trigger event 1 TrOnchip.state Show on-chip trigger window TrOnchip.X Select trigger source X TrOnchip.Y Select trigger source Y Simulator for TriCore 24

25 Support Available Tools CPU ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR PXB4260 YES YES YES TC10GP YES YES YES TC1100 YES YES YES TC1115 YES YES YES TC1124 YES YES TC1128 YES YES TC1130 YES YES YES TC1161 YES YES YES YES TC1162 YES YES YES YES TC1163 YES YES YES YES TC1164 YES YES YES YES TC1165 YES YES YES YES TC1166 YES YES YES YES TC1167 YES YES TC1182 YES YES TC1184 YES YES TC1191 YES YES TC1193 YES YES TC1197 YES YES TC1198 YES YES TC11IA YES YES YES TC11IB YES YES YES TC11IC YES YES YES TC1337 YES YES TC1367 YES YES TC1387 YES YES TC1387ED YES YES TC1724 YES YES TC1724ED YES YES TC1728 YES YES TC1728ED YES YES TC1736 YES YES TC1736ED YES YES TC1746 YES YES Simulator for TriCore 25

26 CPU TC1762 YES YES YES YES TC1764 YES YES YES YES TC1765 YES YES YES TC1766 YES YES YES YES TC1766ED YES YES YES YES TC1767 YES YES TC1767ED YES YES TC1768 YES YES TC1775 YES YES YES TC1782 YES YES TC1782ED YES YES TC1784 YES YES TC1784ED YES YES TC1791 YES YES TC1791ED YES YES TC1792 YES YES YES YES TC1793 YES YES TC1793ED YES YES TC1796 YES YES YES YES TC1796ED YES YES YES YES TC1796L YES YES YES YES TC1797 YES YES TC1797ED YES YES TC1798 YES YES TC1798ED YES YES TC1910 YES YES YES TC1912 YES YES YES TC1920 YES YES YES TC233LP YES YES TC234LP YES YES TC260D YES YES TC260DU YES YES TC264D YES YES TC264DA YES YES YES TC264DE YES YES YES TC264DU YES YES TC265D YES YES TC265DE YES YES YES TC265DU YES YES TC270T YES YES TC270TP YES YES Simulator for TriCore 26 ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR

27 CPU TC270TU YES YES TC275T YES YES TC275TA YES YES YES TC275TE YES YES YES TC275TF YES YES YES TC275TP YES YES TC275TU YES YES TC277T YES YES TC277TA YES YES YES TC277TE YES YES YES TC277TF YES YES YES TC277TP YES YES TC277TU YES YES TC290T YES YES TC290TP YES YES TC290TU YES YES TC297T YES YES TC297TA YES YES YES TC297TE YES YES YES TC297TF YES YES YES TC297TP YES YES TC297TU YES YES TC298T YES YES TC298TE YES YES YES TC298TF YES YES YES TC298TP YES YES TC298TU YES YES TC299T YES YES TC299TE YES YES YES TC299TF YES YES YES TC299TP YES YES TC299TU YES YES TC2D5T YES YES TC2D5TE YES YES YES TC2D7T YES YES TC2D7TE YES YES YES ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR Simulator for TriCore 27

28 Compilers Language Compiler Company Option Comment C/C++ GREENHILLS Greenhills Software Inc. ELF/DWARF2 C/C++ GCC HighTec EDV-Systeme ELF/DWARF2 GmbH C/C++ VX-TC TASKING ELF/DWARF2 C/C++ VX-TC TASKING IEEE C/C++ DIAB Wind River Systems ELF Target Operating Systems Company Product Comment Elektrobit Automotive Elektrobit tresos via ORTI GmbH Evidence Erika via ORTI freertos FreeRTOS Mentor Graphics Nucleus Corporation Vector oscan via ORTI Enea OSE Systems OSE Epsilon - OSEK via ORTI Elektrobit Automotive ProOSEK via ORTI GmbH HighTec EDV-Systeme PXROS-HR GmbH Micrium Inc. uc/os-ii 2.0 to 2.8 Wind River Systems VxWorks 5.x and 6.x Simulator for TriCore 28

29 3rd Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows TA INSPECTOR Timing Architects GmbH Windows UNDODB Undo Software Linux VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE COVERAGE Vector Software Windows Simulator for TriCore 29

30 Products Product Information OrderNo Code LA-2800L SIMULATOR-TC-FL Text 1 User Float. Lic. TRACE32 TriCore Simulator Floating license to use the TRACE32 Instruction Set Simulator for automated tests via script language PRACTICE or via the TRACE32 Remote API supports TriCore for Windows32, Windows64, Linux32, Linux64 and Solaris, other platforms on request floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ) Order Information Order No. Code Text LA-2800L SIMULATOR-TC-FL 1 User Float. Lic. TRACE32 TriCore Simulator Simulator for TriCore 30